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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Clemens Ladisch <clemens@ladisch.de>
Cc: Jimmie Mayfield <mayfield@sackheads.org>, linux-kernel@vger.kernel.org
Subject: Re: Trying to reset a PCIe device and scratching my head...
Date: Tue, 28 Sep 2010 09:06:55 -0700	[thread overview]
Message-ID: <20100928090655.158d1675@jbarnes-desktop> (raw)
In-Reply-To: <4CA1990E.9080206@ladisch.de>

On Tue, 28 Sep 2010 09:28:14 +0200
Clemens Ladisch <clemens@ladisch.de> wrote:

> Jimmie Mayfield wrote:
> > Having the PCIe interface implemented inside FPGA 'A' makes upgrading
> > that particular FPGA rather troublesome.  In a perfect world, one would
> > be able to upgrade the FPGA without having to reboot the machine.  The
> > hardware guys have designed the card to reload that FPGA image upon a
> > slot reset...either fundamental or hot.
> > 
> > So I'd like to be able to send either a fundamental or hot reset to the
> > device but so far I've had no success.
> 
> The PCIe AER driver (drivers/pci/pcie/aer/) sends a hot reset when
> it has received a fatal error.  As far as I can tell, it just sets the
> PCI_BRIDGE_CTL_BUS_RESET bit of the upstream bridge; everything else
> is just infrastructure to handle error reporting and to notify the
> device driver about the reset.

Right, if your system supports this, it may be the easiest way to go.
But devices often have proprietary ways of resetting themselves too;
maybe you could change your device to reset if a specific bit in config
or MMIO space was flipped.  You'd likely need some sort of delay before
accessing the device again, but it should be bounded and fairly fixed,
so probably not a big deal for the driver to handle.

-- 
Jesse Barnes, Intel Open Source Technology Center

  reply	other threads:[~2010-09-28 16:07 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-09-28  2:05 Jimmie Mayfield
2010-09-28  7:28 ` Clemens Ladisch
2010-09-28 16:06   ` Jesse Barnes [this message]
2010-09-28 19:13     ` Jimmie Mayfield

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