From: Ingo Molnar <mingo@elte.hu>
To: Cyrill Gorcunov <gorcunov@openvz.org>,
Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: maciej.rutecki@gmail.com, Shaun Ruffell <sruffell@digium.com>,
Don Zickus <dzickus@redhat.com>,
linux-kernel@vger.kernel.org, Lin Ming <ming.m.lin@intel.com>
Subject: Re: [regression 2.6.39-rc2][bisected] "perf, x86: P4 PMU - Read proper MSR register to catch" and NMIs
Date: Thu, 14 Apr 2011 08:47:37 +0200 [thread overview]
Message-ID: <20110414064737.GB15535@elte.hu> (raw)
In-Reply-To: <4DA6011F.7070405@openvz.org>
* Cyrill Gorcunov <gorcunov@openvz.org> wrote:
> - apic_write(APIC_LVTPC, APIC_DM_NMI);
>
> handled = x86_pmu.handle_irq(args->regs);
> if (!handled)
> return NOTIFY_DONE;
>
> + /*
> + * Unmasking should be done after IRQ handled, otherwise
> + * there is a race between clearing of counter overflow
> + * flag and LTV entry unmasking (which might lead to double
> + * NMIs generation).
> + */
> + apic_write(APIC_LVTPC, APIC_DM_NMI);
Here we could leak a masked IRQ through the !handled path. If we got a LVTPC
irq we better handle it and unmask the LVTPC unconditionally - regardless of
whether we consider it 'handled' or not from the kernel POV ...
Thanks,
Ingo
next prev parent reply other threads:[~2011-04-14 6:47 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-06 22:30 Shaun Ruffell
2011-04-07 0:16 ` Don Zickus
2011-04-07 3:18 ` Cyrill Gorcunov
2011-04-07 14:38 ` Shaun Ruffell
2011-04-07 14:43 ` Cyrill Gorcunov
2011-04-13 19:33 ` Maciej Rutecki
2011-04-13 20:01 ` Cyrill Gorcunov
2011-04-13 20:35 ` Shaun Ruffell
2011-04-13 20:43 ` Cyrill Gorcunov
2011-04-13 21:22 ` Don Zickus
2011-04-13 21:25 ` Cyrill Gorcunov
2011-04-13 21:53 ` Shaun Ruffell
2011-04-14 14:30 ` Shaun Ruffell
2011-04-14 14:33 ` Cyrill Gorcunov
2011-04-14 6:47 ` Ingo Molnar [this message]
2011-04-14 7:51 ` Cyrill Gorcunov
2011-04-14 8:05 ` Ingo Molnar
2011-04-14 9:27 ` Cyrill Gorcunov
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