From: Francois Romieu <romieu@fr.zoreil.com>
To: Su Kang Yin <cantona@cantona.no-ip.org>
Cc: hayeswang <hayeswang@realtek.com>,
linux-kernel@vger.kernel.org, nic_swsd@realtek.com,
netdev@vger.kernel.org
Subject: Re: [PATCH 1/1] r8169.c correct MSIEnable register offset
Date: Wed, 14 Dec 2011 22:37:13 +0100 [thread overview]
Message-ID: <20111214213713.GA2907@electric-eye.fr.zoreil.com> (raw)
In-Reply-To: <CABJLtPHWfRLcbzDFR0ZXe4da3jv04eDZL2CabF1FTcaadoy0xQ@mail.gmail.com>
Su Kang Yin <cantona@cantona.no-ip.org> :
> correct MSIEnable (bit 5) register to Config1 (offset 0x52) instead of
> Config2 (offset 0x53)
I wonder where the inspiration for the MSIEnable bit came from.
It looks like something was confused with the Message Control word
in PCI space.
Imho you can simply remove it altogether.
--
Ueimor
next prev parent reply other threads:[~2011-12-14 21:45 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-14 7:13 Su Kang Yin
2011-12-14 21:37 ` Francois Romieu [this message]
2011-12-15 6:43 ` David Miller
2011-12-15 8:34 ` hayeswang
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