From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752723Ab2AYHjl (ORCPT ); Wed, 25 Jan 2012 02:39:41 -0500 Received: from hqemgate04.nvidia.com ([216.228.121.35]:19861 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752020Ab2AYHjh (ORCPT ); Wed, 25 Jan 2012 02:39:37 -0500 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 24 Jan 2012 23:39:37 -0800 From: Hiroshi Doyu To: "joro@8bytes.org" CC: "balbi@ti.com" , "iommu@lists.linux-foundation.org" , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linaro-mm-sig@lists.linaro.org" Date: Wed, 25 Jan 2012 08:39:32 +0100 Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Thread-Topic: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Thread-Index: AczbNHucYfYLA6PPQWCIWwFnQDjm0Q== Message-ID: <20120125.093932.783007031082378997.hdoyu@nvidia.com> References: <20120124.154121.1062920821192552748.hdoyu@nvidia.com><20120124134601.GT27414@legolas.emea.dhcp.ti.com><20120124142521.GE6269@8bytes.org> In-Reply-To: <20120124142521.GE6269@8bytes.org> Accept-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-nvconfidentiality: public acceptlanguage: en-US Content-Type: multipart/mixed; boundary="_002_20120125093932783007031082378997hdoyunvidiacom_" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --_002_20120125093932783007031082378997hdoyunvidiacom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable From: "joro@8bytes.org" Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Date: Tue, 24 Jan 2012 15:25:21 +0100 Message-ID: <20120124142521.GE6269@8bytes.org> > On Tue, Jan 24, 2012 at 03:46:01PM +0200, Felipe Balbi wrote: > > On Tue, Jan 24, 2012 at 02:41:21PM +0100, Hiroshi Doyu wrote: > > > Actually I really like the concept of this "domain" now, which hides > > > the H/W hierarchy from users. > > >=20 > > > But in Tegra SMMU/GART case, there's a single one IOMMU device in the > > > system. Keeping a iommu device list in a domain and iterating iommu > > > device list in each iommu_ops seem to be so nice, but I'm afraid that > > > this may be a bit too much when one already knows that there's only > > > one IOMMU device in the system. > > > > > > If there's no actual problem for 1-1 mapping between IOMMU H/Ws and > > > domains, I think that it may not so bad to keep the original code(1-1= ) > > > for GART and SMMU. What do you think? > >=20 > > I think it boils down to "extensability". If you can truly/fully > > guarantee that there will *always* be a single IOMMU on all upcoming > > Tegras, then it's really overkill. > >=20 > > But if there's even a remote possibility of the HW being changed and yo= u > > end up with more IOMMUs, things start to feel necessary for the sake of > > making it easy to extend. >=20 > Right. But I am fine with the logic as-is when there is only one SMMU in > the system. But please also change the IOMMU driver so that it really > only initializes a single SMMU. When boards pop up with more than one > you we notice that assumption in the code again and are reminded to > change it. Fixed. I'll revisit 4MB pagesize support and the above multiple iommu device support in a domain later. Attached the update patch. --_002_20120125093932783007031082378997hdoyunvidiacom_ Content-Type: text/x-patch; name="0002-ARM-IOMMU-Tegra30-Add-iommu_ops-for-SMMU-driver.patch" Content-Description: 0002-ARM-IOMMU-Tegra30-Add-iommu_ops-for-SMMU-driver.patch Content-Disposition: attachment; filename="0002-ARM-IOMMU-Tegra30-Add-iommu_ops-for-SMMU-driver.patch"; size=33838; creation-date="Wed, 25 Jan 2012 07:39:34 GMT"; modification-date="Wed, 25 Jan 2012 07:39:34 GMT" Content-Transfer-Encoding: base64 RnJvbSAxODQ0ODQyNGNlMWY4YWU1NTRjZDNiODAxZDYxYjZhMDY0ZTRiY2Q4IE1vbiBTZXAgMTcg MDA6MDA6MDAgMjAwMQ0KRnJvbTogSGlyb3NoaSBET1lVIDxoZG95dUBudmlkaWEuY29tPg0KRGF0 ZTogVGh1LCAxNyBOb3YgMjAxMSAwNzozMTozMSArMDIwMA0KU3ViamVjdDogW1BBVENIIDIvMl0g QVJNOiBJT01NVTogVGVncmEzMDogQWRkIGlvbW11X29wcyBmb3IgU01NVSBkcml2ZXINCg0KVGVn cmEgMzAgSU9NTVUgSC9XLCBTTU1VIChTeXN0ZW0gTWVtb3J5IE1hbmFnZW1lbnQgVW5pdCkuIFRo aXMgcGF0Y2gNCmltcGxlbWVudHMgc3RydWN0IGlvbW11X29wcyBmb3IgU01NVSBmb3IgdGhlIHVw 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