From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752715Ab2AYHk0 (ORCPT ); Wed, 25 Jan 2012 02:40:26 -0500 Received: from hqemgate04.nvidia.com ([216.228.121.35]:19945 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752487Ab2AYHkY (ORCPT ); Wed, 25 Jan 2012 02:40:24 -0500 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Tue, 24 Jan 2012 23:40:24 -0800 From: Hiroshi Doyu To: "joro@8bytes.org" CC: "iommu@lists.linux-foundation.org" , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linaro-mm-sig-bounces@lists.linaro.org" Date: Wed, 25 Jan 2012 08:40:20 +0100 Subject: Re: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver Thread-Topic: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver Thread-Index: AczbNJdaQZ2/qQUkTCqgBusmxqQQjw== Message-ID: <20120125.094020.983282777619146490.hdoyu@nvidia.com> References: <1325747509-29665-1-git-send-email-hdoyu@nvidia.com><1325747509-29665-2-git-send-email-hdoyu@nvidia.com><20120123150048.GB6269@8bytes.org> In-Reply-To: <20120123150048.GB6269@8bytes.org> Accept-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-nvconfidentiality: public acceptlanguage: en-US Content-Type: multipart/mixed; boundary="_002_20120125094020983282777619146490hdoyunvidiacom_" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --_002_20120125094020983282777619146490hdoyunvidiacom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi Joerg, From: Joerg Roedel Subject: Re: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver Date: Mon, 23 Jan 2012 16:00:48 +0100 Message-ID: <20120123150048.GB6269@8bytes.org> > Hi, >=20 > first, some questions about the GART on your platform. >=20 > 1) How many GARTs are usually implemented? One GART per device or is > there a single GART covering all devices, or a mix of both? There's a single GART in the system which takes care of all devices. > 2) Are devices allowed to DMA outside of the remappable range or will > this fail? Fail. >=20 > Besides that I think IOMMU-API is not yet fully ready for GART-like > drivers like this one. But I will merge it anyway to get things moving. > But please answer or fix my objections first. >=20 > On Thu, Jan 05, 2012 at 09:11:48AM +0200, Hiroshi DOYU wrote: > > +static void gart_iommu_domain_destroy(struct iommu_domain *domain) > > +{ > > + struct gart_device *gart =3D domain->priv; > > + > > + spin_lock(&gart->client_lock); > > + if (!list_empty(&gart->client)) { > > + struct gart_client *c; > > + > > + list_for_each_entry(c, &gart->client, list) > > + dev_err(gart->dev, > > + "%s is still attached\n", dev_name(c->dev)); > > + } > > + spin_unlock(&gart->client_lock); >=20 > gart needs a NULL check. When you create a domain and immediatly destroy > it without ever attaching a device this code will dereference a NULL > pointer. Fixed. > As a general improvement I suggest that you introduce a gart_domain > structure and store it in domain->priv (assigned in domain_init) instead > of using the hardware descriptor. >=20 > > +static int gart_iommu_attach_dev(struct iommu_domain *domain, > > + struct device *dev) > > +{ > > + struct gart_device *gart; > > + struct gart_client *client, *c; > > + int err =3D 0; > > + > > + gart =3D dev_get_drvdata(dev->parent); > > + if (!gart) > > + return -EINVAL; > > + domain->priv =3D gart; >=20 > What happens when devices behind different GARTs are assigned to the > same domain? domain->priv can only hold a pointer to one hardware GART. > This can be solved by a 'struct gart_domain' holding a linked list to > all gart_devices in this domain. As discussed in SMMU thread, I'll revisit the above multiple iommu device support later. Attached the update patch. --_002_20120125094020983282777619146490hdoyunvidiacom_ Content-Type: text/x-patch; name="0001-ARM-IOMMU-Tegra20-Add-iommu_ops-for-GART-driver.patch" Content-Description: 0001-ARM-IOMMU-Tegra20-Add-iommu_ops-for-GART-driver.patch Content-Disposition: attachment; filename="0001-ARM-IOMMU-Tegra20-Add-iommu_ops-for-GART-driver.patch"; size=14203; creation-date="Wed, 25 Jan 2012 07:40:21 GMT"; modification-date="Wed, 25 Jan 2012 07:40:21 GMT" Content-Transfer-Encoding: base64 RnJvbSBmNGMxZGJiMGRmZWU3OWVjYjQ0NDM3Nzc3ODA0NzBmNjY5ODA0NGU5IE1vbiBTZXAgMTcg MDA6MDA6MDAgMjAwMQ0KRnJvbTogSGlyb3NoaSBET1lVIDxoZG95dUBudmlkaWEuY29tPg0KRGF0 ZTogV2VkLCAxNiBOb3YgMjAxMSAxNzozNjozNyArMDIwMA0KU3ViamVjdDogW1BBVENIIDEvMl0g QVJNOiBJT01NVTogVGVncmEyMDogQWRkIGlvbW11X29wcyBmb3IgR0FSVCBkcml2ZXINCg0KVGVn cmEgMjAgSU9NTVUgSC9XLCBHQVJUIChHcmFwaGljcyBBZGRyZXNzIFJlbG9jYXRpb24gVGFibGUp LiBUaGlzDQpwYXRjaCBpbXBsZW1lbnRzIHN0cnVjdCBpb21tdV9vcHMgZm9yIEdBUlQgZm9yIHRo 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