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From: Borislav Petkov <bp@amd64.org>
To: Alex Shi <alex.shi@intel.com>
Cc: rob@landley.net, tglx@linutronix.de, mingo@redhat.com,
	hpa@zytor.com, arnd@arndb.de, rostedt@goodmis.org,
	fweisbec@gmail.com, jeremy@goop.org, gregkh@linuxfoundation.org,
	borislav.petkov@amd.com, riel@redhat.com, luto@mit.edu,
	avi@redhat.com, len.brown@intel.com, dhowells@redhat.com,
	fenghua.yu@intel.com, ak@linux.intel.com, cpw@sgi.com,
	steiner@sgi.com, akpm@linux-foundation.org, penberg@kernel.org,
	hughd@google.com, rientjes@google.com,
	kosaki.motohiro@jp.fujitsu.com, n-horiguchi@ah.jp.nec.com,
	paul.gortmaker@windriver.com, trenn@suse.de, tj@kernel.org,
	oleg@redhat.com, axboe@kernel.dk, a.p.zijlstra@chello.nl,
	kamezawa.hiroyu@jp.fujitsu.com, viro@zeniv.linux.org.uk,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 2/7] x86/tlb_info: get last level TLB entry number of CPU
Date: Thu, 10 May 2012 17:58:02 +0200	[thread overview]
Message-ID: <20120510155802.GF32700@aftab.osrc.amd.com> (raw)
In-Reply-To: <1336626013-28413-3-git-send-email-alex.shi@intel.com>

On Thu, May 10, 2012 at 01:00:08PM +0800, Alex Shi wrote:
> For 4KB pages, x86 CPU has 2 or 1 level TLB, first level is data TLB and
> instruction TLB, second level is shared TLB for both data and instructions.
> 
> For hupe page TLB, usually there is just one level and seperated by 2MB/4MB
> and 1GB.
> 
> Although each levels TLB size is important for performance tuning, but for
> genernal and rude optimizing, last level TLB entry number is suitable. And
> in fact, last level TLB always has the biggest entry number.
> 
> This patch will get the biggest TLB entry number and use it in furture TLB
> optimizing.
> 
> For all kinds of x86 vendor friendly, vendor specific code was moved to its
> specific files.
> 
> Signed-off-by: Alex Shi <alex.shi@intel.com>
> ---
>  arch/x86/include/asm/processor.h |   11 +++
>  arch/x86/kernel/cpu/common.c     |   21 ++++++
>  arch/x86/kernel/cpu/cpu.h        |    9 +++
>  arch/x86/kernel/cpu/intel.c      |  141 ++++++++++++++++++++++++++++++++++++++
>  4 files changed, 182 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
> index 4fa7dcc..797faca 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -61,6 +61,17 @@ static inline void *current_text_addr(void)
>  # define ARCH_MIN_MMSTRUCT_ALIGN	0
>  #endif
>  
> +enum tlb_infos {
> +	ENTRIES,
> +	NR_INFO
> +};
> +
> +extern u16 __read_mostly tlb_lli_4k[NR_INFO];
> +extern u16 __read_mostly tlb_lli_2m[NR_INFO];
> +extern u16 __read_mostly tlb_lli_4m[NR_INFO];
> +extern u16 __read_mostly tlb_lld_4k[NR_INFO];
> +extern u16 __read_mostly tlb_lld_2m[NR_INFO];
> +extern u16 __read_mostly tlb_lld_4m[NR_INFO];

Btw, we're only using the tlb_ll[id]_4k arrays in flush_tlb_range and do
not touch 2m or 4m entries. Do you have any future plans for those or
can they simply be removed?

Besides, those arrays contain only the entries count per TLB size. Maybe
turn them into simple variables?

Thanks.

-- 
Regards/Gruss,
Boris.

Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach
GM: Alberto Bozzo
Reg: Dornach, Landkreis Muenchen
HRB Nr. 43632 WEEE Registernr: 129 19551

  parent reply	other threads:[~2012-05-10 15:58 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-05-10  5:00 [PATCH v4 0/7] tlb flush optimization Alex Shi
2012-05-10  5:00 ` [PATCH v4 1/7] x86/tlb: unify TLB_FLUSH_ALL definition Alex Shi
2012-05-10 18:46   ` Rob Landley
2012-05-11 18:33     ` H. Peter Anvin
2012-05-10  5:00 ` [PATCH v4 2/7] x86/tlb_info: get last level TLB entry number of CPU Alex Shi
2012-05-10 14:43   ` Borislav Petkov
2012-05-11  0:33     ` Alex Shi
2012-05-10 15:58   ` Borislav Petkov [this message]
2012-05-11  0:38     ` Alex Shi
2012-05-10  5:00 ` [PATCH v4 3/7] x86/flush_tlb: try flush_tlb_single one by one in flush_tlb_range Alex Shi
2012-05-10  7:53   ` Borislav Petkov
2012-05-10  8:50     ` Alex Shi
2012-05-10 21:42       ` Rob Landley
2012-05-10  8:42   ` Borislav Petkov
2012-05-10  9:04     ` Alex Shi
2012-05-12  8:01       ` Alex Shi
2012-05-13 11:13         ` Borislav Petkov
2012-05-15  1:06           ` Alex Shi
2012-05-15 10:33             ` Borislav Petkov
2012-05-15 11:16               ` Peter Zijlstra
2012-05-15 11:56                 ` Borislav Petkov
2012-05-15 12:00                   ` Peter Zijlstra
2012-05-15 13:58                     ` Alex Shi
2012-05-10  5:00 ` [PATCH v4 4/7] x86/tlb: fall back to flush all when meet a THP large page Alex Shi
2012-05-10  9:29   ` Peter Zijlstra
2012-05-10 10:40     ` Borislav Petkov
2012-05-11  0:44       ` Alex Shi
2012-05-11  9:03         ` Peter Zijlstra
2012-05-11 16:28   ` Andrea Arcangeli
2012-05-12  7:58     ` Alex Shi
2012-05-10  5:00 ` [PATCH v4 5/7] x86/tlb: add tlb flush all factor for specific CPU Alex Shi
2012-05-10  9:35   ` Peter Zijlstra
2012-05-11  0:47     ` Alex Shi
2012-05-10  9:37   ` Peter Zijlstra
2012-05-11  0:48     ` Alex Shi
2012-05-10  9:38   ` Peter Zijlstra
2012-05-10 10:42     ` Borislav Petkov
2012-05-11  0:50       ` Alex Shi
2012-05-11  0:49     ` Alex Shi
2012-05-11  9:04       ` Peter Zijlstra
2012-05-11  9:04         ` Peter Zijlstra
2012-05-11 12:51           ` Alex Shi
2012-05-10  5:00 ` [PATCH v4 6/7] x86/tlb: optimizing flush_tlb_mm Alex Shi
2012-05-10  8:27   ` Peter Zijlstra
2012-05-10  5:00 ` [PATCH v4 7/7] x86/tlb: add tlb_flushall_factor into sysfs for user testing/tuning Alex Shi
2012-05-10  8:27   ` Borislav Petkov
2012-05-11  0:52     ` Alex Shi
2012-05-11  9:51       ` Borislav Petkov
2012-05-11 12:53         ` Alex Shi
2012-05-10 15:13   ` Greg KH
2012-05-11  0:59     ` Alex Shi

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