From: Peter Zijlstra <peterz@infradead.org>
To: "Yan, Zheng" <zheng.z.yan@intel.com>
Cc: linux-kernel@vger.kernel.org, mingo@elte.hu, eranian@google.com,
ak@linux.intel.com
Subject: Re: [PATCH] perf, x86: Add Silvermont (22nm Atom) support
Date: Thu, 18 Jul 2013 10:41:29 +0200 [thread overview]
Message-ID: <20130718084129.GC27075@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1374125767-9411-1-git-send-email-zheng.z.yan@intel.com>
On Thu, Jul 18, 2013 at 01:36:07PM +0800, Yan, Zheng wrote:
> @@ -1305,7 +1452,7 @@ static void intel_fixup_er(struct perf_event *event, int idx)
> event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
> } else if (idx == EXTRA_REG_RSP_1) {
> event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
> - event->hw.config |= 0x01bb;
> + event->hw.config |= x86_pmu.extra_regs[1].event;
> event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
> }
> }
When you do the split up, please make this consistent and use
x86_pmu.extra_regs[0].event as well.
Also, ideally we'd use EXTRA_REG_RSP_[01] instead of the 0 and 1.
prev parent reply other threads:[~2013-07-18 8:41 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-18 5:36 Yan, Zheng
2013-07-18 5:39 ` Yan, Zheng
2013-07-18 8:42 ` Peter Zijlstra
2013-07-18 11:00 ` Yan, Zheng
2013-07-18 8:23 ` Peter Zijlstra
2013-07-18 8:27 ` Yan, Zheng
2013-07-18 9:02 ` Peter Zijlstra
2013-07-18 10:48 ` Yan, Zheng
2013-07-18 11:46 ` Peter Zijlstra
2013-07-19 2:26 ` Yan, Zheng
2013-07-18 8:29 ` Peter Zijlstra
2013-07-18 8:41 ` Peter Zijlstra [this message]
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