From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Mathias Nyman <mathias.nyman@linux.intel.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
Subject: Re: [PATCH] x86: add pin control support to Intel low power subsystem
Date: Fri, 13 Sep 2013 23:07:16 +0300 [thread overview]
Message-ID: <20130913200716.GH7393@intel.com> (raw)
In-Reply-To: <1379080949-21734-1-git-send-email-mathias.nyman@linux.intel.com>
On Fri, Sep 13, 2013 at 05:02:29PM +0300, Mathias Nyman wrote:
> x86 chips with LPSS (low power subsystem) such as Lynxpoint and
> Baytrail have SoC like peripheral support and controllable pins.
>
> At the moment, Baytrail needs the pinctrl-baytrail driver to let
> peripherals control their gpio resources, but more pincontrol functions
> such as pin muxing and grouping are possible to add later.
>
> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Makes sense, and since there seems to be no way to enable pinctrl by
just selecting it from 'make XXXconfig',
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
next prev parent reply other threads:[~2013-09-13 20:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-13 14:02 Mathias Nyman
2013-09-13 20:07 ` Mika Westerberg [this message]
2013-09-14 7:01 ` [tip:x86/urgent] x86/intel/lpss: Add " tip-bot for Mathias Nyman
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