Re: x86, perf: throttling issues with long nmi latencies

[Peter Zijlstra <peterz@infradead.org>]

On Tue, Oct 15, 2013 at 12:14:04PM +0200, Peter Zijlstra wrote:
>  arch/x86/kernel/cpu/perf_event_intel_ds.c | 43 ++++++++++++++++++++++---------
>  1 file changed, 31 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> index 32e9ed81cd00..3978e72a1c9f 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> @@ -722,6 +722,8 @@ void intel_pmu_pebs_disable_all(void)
>  		wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
>  }
>  
> +static DEFINE_PER_CPU(u8 [PAGE_SIZE], insn_page);
> +
>  static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
>  {
>  	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
> @@ -729,6 +731,8 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
>  	unsigned long old_to, to = cpuc->lbr_entries[0].to;
>  	unsigned long ip = regs->ip;
>  	int is_64bit = 0;
> +	int size, bytes;
> +	void *kaddr;
>  
>  	/*
>  	 * We don't need to fixup if the PEBS assist is fault like
> @@ -763,29 +767,44 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
>  		return 1;
>  	}
>  
> +refill:
> +	if (kernel_ip(ip)) {
> +		u8 *buf = &__get_cpu_var(insn_page[0]);
> +		size = PAGE_SIZE - ((unsigned long)to & (PAGE_SIZE-1));
> +		if (size < MAX_INSN_SIZE) {
> +			/*
> +			 * If we're going to have to touch two pages; just copy
> +			 * as much as we can hold.
> +			 */
> +			size = PAGE_SIZE;


Arguably we'd want that to be:

			size = min(PAGE_SIZE, ip - to);

As there's no point in copying beyond the basic block.

> +		}
> +		bytes = copy_from_user_nmi(buf, (void __user *)to, size);
> +		if (bytes != size)
> +			return 0;
> +
> +		kaddr = buf;