From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760275Ab3JPJGv (ORCPT ); Wed, 16 Oct 2013 05:06:51 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:10457 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757547Ab3JPJGq (ORCPT ); Wed, 16 Oct 2013 05:06:46 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 16 Oct 2013 02:02:20 -0700 Date: Wed, 16 Oct 2013 12:06:43 +0300 From: Peter De Schrijver To: Stephen Warren CC: Prashant Gaikwad , Mike Turquette , Thierry Reding , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Hiroshi Doyu , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: Re: [PATCH v3 00/19] Introduce common infra for tegra clocks Message-ID: <20131016090643.GI5643@tbergstrom-lnx.Nvidia.com> References: <1381848794-11761-1-git-send-email-pdeschrijver@nvidia.com> <525D8009.5040907@wwwdotorg.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <525D8009.5040907@wwwdotorg.org> X-NVConfidentiality: public User-Agent: Mutt/1.5.20 (2009-06-14) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 15, 2013 at 07:48:57PM +0200, Stephen Warren wrote: > On 10/15/2013 08:52 AM, Peter De Schrijver wrote: > > This patchset introduces common infrastructure for clocks which exist in > > several Tegra SoCs. We also also move Tegra20, Tegra30 and Tegra114 to > > this new infrastructure. > > I took my local branch based on next-20131014, and applied the following: > > * Joseph's "ARM: tegra: add clock properties for devices of Tegra124". > > * The patches from your "pull request for tegra clocks" of today (I just > cherry-picked the commits rather than merging the pull request). > > * Your patch series "Introduce common infra for tegra clocks" of today. > > * Your patch series "Tegra124 clock support" of today. > > The resultant branch is at: > git://github.com:swarren/linux-tegra.git linux-next_common > > When building, I see a number of section mismatches: > > > WARNING: drivers/clk/tegra/built-in.o(.text+0x534): Section mismatch in reference from the function _tegra_clk_register_periph() to the function .init.text:get_reg_bank() > > The function _tegra_clk_register_periph() references > > the function __init get_reg_bank(). > > This is often because _tegra_clk_register_periph lacks a __init > > annotation or the annotation of get_reg_bank is wrong. > > > > WARNING: drivers/clk/tegra/built-in.o(.text+0x9ec): Section mismatch in reference from the function tegra_clk_register_periph_gate() to the function .init.text:get_reg_bank() > > The function tegra_clk_register_periph_gate() references > > the function __init get_reg_bank(). > > This is often because tegra_clk_register_periph_gate lacks a __init > > annotation or the annotation of get_reg_bank is wrong. > > There are more, but they refer to references from the same two > functions. You may need to add CONFIG_DEBUG_SECTION_MISMATCH=y to > .config to see these; I can't remember if that's included in > tegra_defconfig. > > Testing on Venice2 (Tegra124): I see the following WARN during boot, > which I think is new relative to the internal branch you gave me yesterday: > > > [ 0.295386] ------------[ cut here ]------------ > > [ 0.300450] WARNING: CPU: 0 PID: 1 at drivers/clk/tegra/clk.c:187 tegra_init_from_table+0x78/0x158() > > [ 0.310362] Modules linked in: > > [ 0.313740] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.0-rc5-next-20131014-05418-g30b9d55 #48 > > [ 0.323397] [] (unwind_backtrace+0x0/0x138) from [] (show_stack+0x10/0x14) > > [ 0.332753] [] (show_stack+0x10/0x14) from [] (dump_stack+0x80/0xc0) > > [ 0.341559] [] (dump_stack+0x80/0xc0) from [] (warn_slowpath_common+0x64/0x88) > > [ 0.351283] [] (warn_slowpath_common+0x64/0x88) from [] (warn_slowpath_null+0x1c/0x24) > > [ 0.361768] [] (warn_slowpath_null+0x1c/0x24) from [] (tegra_init_from_table+0x78/0x158) > > [ 0.372440] [] (tegra_init_from_table+0x78/0x158) from [] (tegra_clocks_apply_init_table+0x18/0x20) > > [ 0.384138] [] (tegra_clocks_apply_init_table+0x18/0x20) from [] (tegra_dt_init+0xc/0xd8) > > [ 0.394903] [] (tegra_dt_init+0xc/0xd8) from [] (customize_machine+0x1c/0x40) > > [ 0.404535] [] (customize_machine+0x1c/0x40) from [] (do_one_initcall+0xec/0x19c) > > [ 0.414551] [] (do_one_initcall+0xec/0x19c) from [] (kernel_init_freeable+0xfc/0x1c8) > > [ 0.424944] [] (kernel_init_freeable+0xfc/0x1c8) from [] (kernel_init+0x8/0xe4) > > [ 0.434764] [] (kernel_init+0x8/0xe4) from [] (ret_from_fork+0x14/0x3c) > > [ 0.443850] ---[ end trace 98c2207379d4cf99 ]--- > Did you see 'tegra_init_from_table: Failed to set parent pll_c2 of epp ' before? Tegra124 doesn't have EPP... Cheers, Peter.