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From: Mark Rutland <mark.rutland@arm.com>
To: "tthayer@altera.com" <tthayer@altera.com>
Cc: "robherring2@gmail.com" <robherring2@gmail.com>,
	"dougthompson@xmission.com" <dougthompson@xmission.com>,
	"grant.likely@linaro.org" <grant.likely@linaro.org>,
	Pawel Moll <Pawel.Moll@arm.com>,
	"ijc+devicetree@hellion.org.uk" <ijc+devicetree@hellion.org.uk>,
	"galak@codeaurora.org" <galak@codeaurora.org>,
	"rob@landley.net" <rob@landley.net>,
	"linux@arm.linux.org.uk" <linux@arm.linux.org.uk>,
	"dinguyen@altera.com" <dinguyen@altera.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC
Date: Tue, 8 Apr 2014 11:51:23 +0100	[thread overview]
Message-ID: <20140408105123.GC11876@e106331-lin.cambridge.arm.com> (raw)
In-Reply-To: <1396907649-20212-3-git-send-email-tthayer@altera.com>

On Mon, Apr 07, 2014 at 10:54:08PM +0100, tthayer@altera.com wrote:
> From: Thor Thayer <tthayer@altera.com>
> 
> Addition of the Altera SDRAM EDAC bindings and device
> tree changes to the Altera SoC project.
> 
> Signed-off-by: Thor Thayer <tthayer@altera.com>
> To: Rob Herring <robherring2@gmail.com>
> To: Pawel Moll <pawel.moll@arm.com>
> To: Mark Rutland <mark.rutland@arm.com>
> To: Ian Campbell <ijc+devicetree@hellion.org.uk>
> To: Kumar Gala <galak@codeaurora.org>
> To: Rob Landley <rob@landley.net>
> To: Russell King <linux@arm.linux.org.uk>
> To: Dinh Nguyen <dinguyen@altera.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> ---
>  .../bindings/arm/altera/socfpga-sdram-edac.txt     |   12 ++++++++++++
>  arch/arm/boot/dts/socfpga.dtsi                     |    5 +++++
>  2 files changed, 17 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
> new file mode 100644
> index 0000000..9348c53
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
> @@ -0,0 +1,12 @@
> +Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
> +
> +Required properties:
> +- compatible : should contain "altr,sdr-edac";
> +- interrupts : Should contain the SDRAM ECC IRQ in the
> +	appropriate format for the IRQ controller.
> +
> +Example:
> +	sdramedac@0 {

Nit: If there's no reg, there shouldn't be a unit-address (the "@0").

> +		compatible = "altr,sdram-edac";
> +		interrupts = <0 39 4>;
> +	};

No phandle to the actual SDRAM controller node? Is there a guaranteed
limitation of a single SDRAM controller?

I don't see the point in describing this separately from the main SDRAM
controller node, given this seems to be a subcomponent.

> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index 6ce912e..a0ea69b 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -681,6 +681,11 @@
>  			reg = <0xffc25000 0x1000>;
>  		};
>  
> +		sdramedac@0 {

Nit: get rid of the unit-address here too.

Cheers,
Mark.

> +			compatible = "altr,sdram-edac";
> +			interrupts = <0 39 4>;
> +		};
> +
>  		rstmgr@ffd05000 {
>  			compatible = "altr,rst-mgr";
>  			reg = <0xffd05000 0x1000>;
> -- 
> 1.7.9.5
> 
> 

  reply	other threads:[~2014-04-08 10:51 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1396907649-20212-1-git-send-email-tthayer@altera.com>
2014-04-07 21:54 ` [PATCH 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller tthayer
2014-04-08 10:48   ` Mark Rutland
2014-04-08 13:38   ` Steffen Trumtrar
2014-04-08 14:29     ` Thor Thayer
2014-04-08 14:33       ` Steffen Trumtrar
2014-04-08 16:02         ` delicious quinoa
2014-04-08 18:52           ` Rob Herring
2014-04-11 14:21             ` Thor Thayer
2014-04-11 14:43             ` Thor Thayer
2014-04-11 14:49             ` Thor Thayer
2014-07-10 21:02             ` Alan Tull
2014-04-07 21:54 ` [PATCH 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC tthayer
2014-04-08 10:51   ` Mark Rutland [this message]
2014-04-07 21:54 ` [PATCH 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV tthayer
2014-04-08 10:08   ` Borislav Petkov
2014-04-08 13:57     ` Thor Thayer
2014-04-08 15:24       ` Borislav Petkov
2014-04-08 15:40         ` Mark Rutland
2014-04-08 16:03           ` Borislav Petkov
2014-04-08 16:10             ` Mark Rutland
2014-04-08 16:22               ` Borislav Petkov
2014-04-08 21:15                 ` Thor Thayer
2014-04-08 10:45   ` Mark Rutland
2014-04-08 12:45     ` Steffen Trumtrar
2014-04-08 14:00       ` Thor Thayer

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