From: Mark Brown <broonie@kernel.org>
To: Chew Chiau Ee <chiau.ee.chew@intel.com>
Cc: Eric Miao <eric.y.miao@gmail.com>,
Russell King <linux@arm.linux.org.uk>,
Haojian Zhuang <haojian.zhuang@gmail.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] spi/pxa2xx-pci: Add PCI mode support for BayTrail LPSS SPI
Date: Fri, 18 Apr 2014 18:06:22 +0100 [thread overview]
Message-ID: <20140418170622.GM12304@sirena.org.uk> (raw)
In-Reply-To: <1397751967-20250-2-git-send-email-chiau.ee.chew@intel.com>
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On Fri, Apr 18, 2014 at 12:26:06AM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
>
> Similar to CE4100, BayTrail LPSS SPI can be PCI enumerated
> as well. Thus, the functions are renamed from ce4100_xxx
Applied, thanks.
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next prev parent reply other threads:[~2014-04-18 17:07 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-17 16:26 [PATCH 0/2] " Chew Chiau Ee
2014-04-17 16:26 ` [PATCH 1/2] spi/pxa2xx-pci: " Chew Chiau Ee
2014-04-18 17:06 ` Mark Brown [this message]
2014-04-17 16:26 ` [PATCH 2/2] spi/pxa2xx-pci: Pass host clock rate info from PCI glue layer Chew Chiau Ee
2014-04-18 16:30 ` Mark Brown
2014-04-22 11:57 ` Mika Westerberg
2014-04-22 12:09 ` Mark Brown
2014-04-22 12:37 ` Mika Westerberg
2014-04-22 14:27 ` One Thousand Gnomes
2014-04-22 18:21 ` Mark Brown
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