From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755134AbaEMXiS (ORCPT ); Tue, 13 May 2014 19:38:18 -0400 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:47410 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752032AbaEMXiQ (ORCPT ); Tue, 13 May 2014 19:38:16 -0400 Date: Wed, 14 May 2014 00:36:45 +0100 From: Russell King - ARM Linux To: Nicolas Pitre Cc: Stephen Warren , Doug Anderson , Viresh Kumar , "Rafael J. Wysocki" , Will Deacon , John Stultz , David Riley , "olof@lixom.net" , Sonny Rao , Santosh Shilimkar , Shawn Guo , Stephen Boyd , Marc Zyngier , Stephen Warren , Paul Gortmaker , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH] ARM: Don't ever downscale loops_per_jiffy in SMP systems# Message-ID: <20140513233645.GN3693@n2100.arm.linux.org.uk> References: <20140509091824.GL3693@n2100.arm.linux.org.uk> <20140509182245.GM3693@n2100.arm.linux.org.uk> <5372998F.6020502@wwwdotorg.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 13, 2014 at 07:29:52PM -0400, Nicolas Pitre wrote: > On Tue, 13 May 2014, Nicolas Pitre wrote: > > > On Tue, 13 May 2014, Stephen Warren wrote: > > > > > On 05/13/2014 03:50 PM, Doug Anderson wrote: > > > ... > > > > ...but then I found the true problem shows up when we transition > > > > between very low frequencies on exynos, like between 200MHz and > > > > 300MHz. While transitioning between frequencies the system > > > > temporarily bumps over to the "switcher" PLL running at 800MHz while > > > > waiting for the main PLL to stabilize. No CPUFREQ notification is > > > > sent for that. That means there's a period of time when we're running > > > > at 800MHz but loops_per_jiffy is calibrated at between 200MHz and > > > > 300MHz. > > > > > > > > > > > > I'm welcome to any suggestions for how to address this. It sorta > > > > feels like it would be a common thing to have a temporary PLL during > > > > the transition, ... > > > > > > We definitely do that on Tegra for some cpufreq transitions. > > > > Ouch... If this is a common strategy to use a third frequency during a > > transition phase, especially if that frequency is way off (800MHz vs > > 200-300MHz) then it is something the cpufreq layer must capture and > > advertise. > > Of course if only the loops_per_jiffy scaling does care about frequency > changes these days, and if in those cases udelay() can instead be moved > to a timer source on those hick-up prone platforms, then all this is > fairly theoretical and may not be worth pursuing. As I've been saying... use a bloody timer. :) -- FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly improving, and getting towards what was expected from it.