From: Mark Brown <broonie@kernel.org>
To: Chew Chiau Ee <chiau.ee.chew@intel.com>
Cc: Eric Miao <eric.y.miao@gmail.com>,
Russell King <linux@arm.linux.org.uk>,
Haojian Zhuang <haojian.zhuang@gmail.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
LKML <linux-kernel@vger.kernel.org>,
linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org
Subject: Re: [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
Date: Thu, 12 Jun 2014 00:42:12 +0100 [thread overview]
Message-ID: <20140611234212.GR5099@sirena.org.uk> (raw)
In-Reply-To: <1402502222-19520-1-git-send-email-chiau.ee.chew@intel.com>
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On Wed, Jun 11, 2014 at 11:57:02PM +0800, Chew Chiau Ee wrote:
> It was observed that after module removal followed by insertion,
> the SW mode chipselect is not properly set. Thus causing transfer
> failure due to incorrect CS toggling.
> - value &= ~SPI_CS_CONTROL_SW_MODE;
> + orig = value &= ~SPI_CS_CONTROL_SW_MODE;
> writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
> value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
> if (value != orig) {
This is a *really* non-obvious fix, I'd have expected the original value
to be re-read from the hardware here rather than just tweaked, or at
least some comment explaining what's going on. Possibly also saving to
a differently named temporary variable would do it but whatever I had to
go look at the context to figure out what was happening and even there I
was unclear.
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prev parent reply other threads:[~2014-06-11 23:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-11 15:57 Chew Chiau Ee
2014-06-11 23:42 ` Mark Brown [this message]
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