From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Chew Chiau Ee <chiau.ee.chew@intel.com>
Cc: Eric Miao <eric.y.miao@gmail.com>,
Russell King <linux@arm.linux.org.uk>,
Haojian Zhuang <haojian.zhuang@gmail.com>,
Mark Brown <broonie@kernel.org>,
linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
Date: Fri, 13 Jun 2014 16:10:08 +0300 [thread overview]
Message-ID: <20140613131008.GK21178@lahna.fi.intel.com> (raw)
In-Reply-To: <1402675045-22460-1-git-send-email-chiau.ee.chew@intel.com>
On Fri, Jun 13, 2014 at 11:57:25PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
>
> It was observed that after module removal followed by insertion,
> the SW mode chipselect is not properly set. Thus causing transfer
> failure due to incorrect CS toggling.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
next prev parent reply other threads:[~2014-06-13 13:10 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-13 15:57 Chew Chiau Ee
2014-06-13 13:10 ` Mika Westerberg [this message]
2014-06-17 14:46 ` Mark Brown
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