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From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: Konstantin Khlebnikov <koct9i@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>,
	Konstantin Khlebnikov <k.khlebnikov@samsung.com>,
	Vitaly Andrianov <vitalya@ti.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	Cyril Chemparathy <cyril@ti.com>
Subject: Re: [PATCH 2/2] ARM: LPAE: reduce damage caused by idmap to virtual memory layout
Date: Mon, 28 Jul 2014 20:42:51 +0100	[thread overview]
Message-ID: <20140728194251.GB30282@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <CALYGNiNVduTK8MXt8VJyiqdsB0mA_OnC0hLOB-WzgAEMZyu9sg@mail.gmail.com>

On Mon, Jul 28, 2014 at 11:29:39PM +0400, Konstantin Khlebnikov wrote:
> Ok, before switching from identity mapping to normal mapping kernel must
> switch instruction pointer from physical address to virtual.

"switch instruction pointer from physical address to virtual."

There's no such distinction for the instruction pointer.

There is the mode where the MMU is disabled.  The CPU fetches from the
address in the program counter.  The instructions it fetches will
instruct it to perform operations to enable the MMU.

The CPU itself continues fetching instructions (with an unpredictable
number of instructions in the CPU's pipeline) across this boundary.

Hence, it is _impossible_ to know which exact instructions are fetched
with the MMU off, and which are fetched with the MMU on.

This is why we need the identity mapping: so that the CPU's instruction
fetches can continue unaffected by turning the MMU on.

Before the MMU is on, the CPU is fetching from an untranslated (== physical)
view of the address space, which is limited to 4GB in size.

After the MMU is on, the CPU is fetching from a translated (== virtual)
view of the address space, which and the translated version is also
limited to 4GB in size.

> It's a long jump
> out idmap code section to some normal kernel function.
> __secondary_switched in my case. And both physical source and virtual
> destination addresses must present in one same mapping (idmap).

... one which the code already caters for.

> idmap pgd starts as copy of pgd from init_mm, it points to the same pmd pages.
> When it populates identical mapping for that special code section it allocates
> new pages from pmd entries (which covers 1Gb of vm layout) but only few of
> them are filled. In case 3/1GB split If idmap touches somehing above 3Gb it
> kills whole kernel vm layout and as result kernel cannot jump to any
> virtual address.

It doesn't matter, provided the kernel text and data in the virtual
address space are not overwritten by the identity mapping.  If it
ends up in the vmalloc or IO space, that should not be a problem.

It also should not be a problem if the physical memory starts at
PAGE_OFFSET (iow, PHYS_OFFSET == PAGE_OFFSET).  Indeed, we have
some platforms where that is true.

-- 
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.

  parent reply	other threads:[~2014-07-28 19:43 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-22 15:36 [PATCH 1/2] ARM: LPAE: load upper bits of early TTBR0/TTBR1 Konstantin Khlebnikov
2014-07-22 15:36 ` [PATCH 2/2] ARM: LPAE: reduce damage caused by idmap to virtual memory layout Konstantin Khlebnikov
2014-07-28 18:14   ` Will Deacon
2014-07-28 18:25     ` Konstantin Khlebnikov
2014-07-28 18:41       ` Will Deacon
2014-07-28 18:57         ` Konstantin Khlebnikov
2014-07-28 19:06           ` Will Deacon
2014-07-28 19:13           ` Russell King - ARM Linux
2014-07-28 19:29             ` Konstantin Khlebnikov
2014-07-28 19:34               ` Konstantin Khlebnikov
2014-07-28 19:42               ` Russell King - ARM Linux [this message]
2014-07-28 19:57                 ` Konstantin Khlebnikov
2014-07-29 10:57                   ` Russell King - ARM Linux
2014-07-29 12:37                     ` Konstantin Khlebnikov
2014-07-28 18:12 ` [PATCH 1/2] ARM: LPAE: load upper bits of early TTBR0/TTBR1 Will Deacon
2014-07-28 18:40   ` Konstantin Khlebnikov
2014-07-28 18:47     ` Will Deacon
2014-07-29 11:15       ` Will Deacon
2014-07-29 12:29       ` Konstantin Khlebnikov
2014-08-27 15:26         ` Jassi Brar
2014-08-27 15:31           ` Konstantin Khlebnikov
2014-08-27 15:33             ` Konstantin Khlebnikov
2014-08-27 15:45             ` Jassi Brar
2014-08-28 11:03               ` Will Deacon
2014-08-28 11:50                 ` Konstantin Khlebnikov
2014-08-05 15:42 ` Konstantin Khlebnikov

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