From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754269AbaIKKYn (ORCPT ); Thu, 11 Sep 2014 06:24:43 -0400 Received: from mail-wg0-f48.google.com ([74.125.82.48]:44265 "EHLO mail-wg0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754248AbaIKKYl (ORCPT ); Thu, 11 Sep 2014 06:24:41 -0400 From: Grant Likely Subject: Re: [PATCH v3 09/17] ARM64 / ACPI: Parse MADT for SMP initialization To: Hanjun Guo , Catalin Marinas , "Rafael J. Wysocki" , Mark Rutland , Olof Johansson Cc: Graeme Gregory , Arnd Bergmann , Sudeep Holla , Will Deacon , Jason Cooper , Marc Zyngier , Bjorn Helgaas , Daniel Lezcano , Mark Brown , Rob Herring , Robert Richter , Lv Zheng , Robert Moore , Lorenzo Pieralisi , Liviu Dudau , Randy Dunlap , Charles.Garcia-Tobin@arm.com, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linaro-acpi@lists.linaro.org, Hanjun Guo , Tomasz Nowicki In-Reply-To: <1409583475-6978-10-git-send-email-hanjun.guo@linaro.org> References: <1409583475-6978-1-git-send-email-hanjun.guo@linaro.org> <1409583475-6978-10-git-send-email-hanjun.guo@linaro.org> Date: Thu, 11 Sep 2014 11:24:36 +0100 Message-Id: <20140911102436.B6671C40862@trevor.secretlab.ca> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 1 Sep 2014 22:57:47 +0800, Hanjun Guo wrote: > MADT contains the information for MPIDR which is essential for > SMP initialization, parse the GIC cpu interface structures to > get the MPIDR value and map it to cpu_logical_map(), and add > enabled cpu with valid MPIDR into cpu_possible_map. > > ACPI 5.1 only has two explicit methods to boot up SMP, PSCI and > Parking protocol, but the Parking protocol is only specified for > ARMv7 now, so make PSCI as the only way for the SMP boot protocol > before some updates for the ACPI spec or the Parking protocol spec. > > Signed-off-by: Hanjun Guo > Signed-off-by: Tomasz Nowicki > --- > +/** > + * acpi_map_gic_cpu_interface - generates a logical cpu number > + * and map to MPIDR represented by GICC structure > + * @mpidr: CPU's hardware id to register, MPIDR represented in MADT > + * @enabled: this cpu is enabled or not > + * > + * Returns the logical cpu number which maps to MPIDR > + */ > +static int acpi_map_gic_cpu_interface(u64 mpidr, u8 enabled) > +{ > + int cpu; > + > + if (mpidr == INVALID_HWID) { > + pr_info("Skip invalid cpu hardware ID\n"); > + return -EINVAL; > + } > + > + total_cpus++; > + if (!enabled) > + return -EINVAL; > + > + if (enabled_cpus >= NR_CPUS) { > + pr_warn("NR_CPUS limit of %d reached, Processor %d/0x%llx ignored.\n", > + NR_CPUS, total_cpus, mpidr); > + return -EINVAL; > + } > + > + /* No need to check duplicate MPIDRs for the first CPU */ > + if (enabled_cpus) { > + /* > + * Duplicate MPIDRs are a recipe for disaster. Scan > + * all initialized entries and check for > + * duplicates. If any is found just ignore the CPU. > + */ > + for_each_possible_cpu(cpu) { > + if (cpu_logical_map(cpu) == mpidr) { > + pr_err("Firmware bug, duplicate CPU MPIDR: 0x%llx in MADT\n", > + mpidr); > + return -EINVAL; > + } > + } > + } else { > + /* Fist GICC entry must be BSP as ACPI spec said */ > + if (cpu_logical_map(0) != mpidr) { > + pr_err("First GICC entry is not BSP for MPIDR 0x%llx\n", > + mpidr); > + return -EINVAL; > + } > + } > + > + /* allocate a logical cpu id for the new comer */ > + if (cpu_logical_map(0) == mpidr) { > + /* > + * boot_cpu_init() already hold bit 0 in cpu_present_mask > + * for BSP, no need to allocate again. > + */ > + cpu = 0; > + } else { > + cpu = cpumask_next_zero(-1, cpu_possible_mask); > + } Nit: so the above two if/else blocks are essentially testing for the same condition: Is this the first cpu? or a secondary cpu? I would merge the two into a single if/else block. g.