From: Jason Cooper <jason@lakedaemon.net>
To: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Boris Brezillon <boris.brezillon@free-electrons.com>,
Nicolas Ferre <nicolas.ferre@atmel.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] irqchip: atmel-aic5: sama5d3 has 48 IRQs
Date: Sun, 14 Sep 2014 02:36:20 -0400 [thread overview]
Message-ID: <20140914063620.GM21986@titan.lakedaemon.net> (raw)
In-Reply-To: <1410446511-29477-1-git-send-email-alexandre.belloni@free-electrons.com>
On Thu, Sep 11, 2014 at 04:41:51PM +0200, Alexandre Belloni wrote:
> The FUSE and RAM controllers don't have any connected IRQs, reducing the number
> of IRQs to 48.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> drivers/irqchip/irq-atmel-aic5.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to irqchip/atmel with Boris' and Nicolas' Acks.
thx,
Jason.
prev parent reply other threads:[~2014-09-14 6:36 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-11 14:41 Alexandre Belloni
2014-09-11 15:06 ` Boris BREZILLON
2014-09-11 16:27 ` Nicolas Ferre
2014-09-14 6:36 ` Jason Cooper [this message]
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