From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757238AbaIRVCY (ORCPT ); Thu, 18 Sep 2014 17:02:24 -0400 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:33774 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756203AbaIRVCX (ORCPT ); Thu, 18 Sep 2014 17:02:23 -0400 Date: Thu, 18 Sep 2014 22:02:12 +0100 From: Russell King - ARM Linux To: Alexandre Belloni Cc: Nicolas Ferre , Jean-Christophe Plagniol-Villard , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Wenyou Yang Subject: Re: [PATCH] ARM: at91: sama5: configure L2 cache Message-ID: <20140918210212.GD5182@n2100.arm.linux.org.uk> References: <1411072716-20769-1-git-send-email-alexandre.belloni@free-electrons.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1411072716-20769-1-git-send-email-alexandre.belloni@free-electrons.com> User-Agent: Mutt/1.5.19 (2009-01-05) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 18, 2014 at 10:38:36PM +0200, Alexandre Belloni wrote: > From: Wenyou Yang > > Ensure that the L2 cache configuration is optimal to avoid depending on the > bootloader to set it correctly. > > Signed-off-by: Wenyou Yang > Signed-off-by: Alexandre Belloni > --- > arch/arm/mach-at91/board-dt-sama5.c | 47 ++++++++++++++++++++++++++++++++++++- > 1 file changed, 46 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c > index 548de4ad6937..7cbe0d9daf2b 100644 > --- a/arch/arm/mach-at91/board-dt-sama5.c > +++ b/arch/arm/mach-at91/board-dt-sama5.c > @@ -13,12 +13,14 @@ > #include > #include > #include > +#include > #include > #include > #include > #include > > #include > +#include > #include > #include > #include > @@ -35,8 +37,52 @@ static void __init sama5_dt_timer_init(void) > at91sam926x_pit_init(); > } > > +static void __init at91_l2x0_init(void) > +{ > + struct device_node *np; > + void __iomem *l2cc_base; > + u32 reg; > + > + np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); > + if (!np) > + return; > + > + l2cc_base = of_iomap(np, 0); > + of_node_put(np); > + > + if (!l2cc_base) { > + pr_err("L2C-310 unable to map registers\n"); > + return; > + } > + > + /* Prefetch Control */ > + reg = readl_relaxed(l2cc_base + L310_PREFETCH_CTRL); > + reg &= ~L310_PREFETCH_CTRL_OFFSET_MASK; > + reg |= 0x01 & L310_PREFETCH_CTRL_OFFSET_MASK; > + reg |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR; > + reg |= L310_PREFETCH_CTRL_PREFETCH_DROP; > + reg |= L310_PREFETCH_CTRL_DATA_PREFETCH; > + reg |= L310_PREFETCH_CTRL_INSTR_PREFETCH; > + reg |= L310_PREFETCH_CTRL_DBL_LINEFILL; > + writel_relaxed(reg, l2cc_base + L310_PREFETCH_CTRL); > + > + /* Power Control */ > + reg = readl_relaxed(l2cc_base + L310_POWER_CTRL); > + reg |= L310_STNDBY_MODE_EN; > + reg |= L310_DYNAMIC_CLK_GATING_EN; > + writel_relaxed(reg, l2cc_base + L310_POWER_CTRL); > + > + /* Disable interrupts */ > + writel_relaxed(0x00, l2cc_base + L2X0_INTR_MASK); > + writel_relaxed(0x01ff, l2cc_base + L2X0_INTR_CLEAR); > + > + l2x0_of_init(0, ~0UL); NAK. Really, nak. Stop this mentality of working around shortcomings of generic code by adding yet more platform junk. Such approaches are not acceptable. The power control is already done by generic code. I know that you've developed the above code against the exact copy of generic code which has this, because you're using the new symbols. You shouldn't need to disable interrupts; the interrupts should already be disabled unless your bootloaders are doing something weird with them. There have been DT bindings proposed for prefetch control register. I suggest that you search this mailing list for that patch, and check whether it is acceptable for your platform. Taking all that together, you should need /zero/ code in your platform for L2 caches, which is *the way it should be*. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net.