From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
To: David Laight <David.Laight@ACULAB.COM>
Cc: Cyrille Pitchen <cyrille.pitchen@atmel.com>,
"nicolas.ferre@atmel.com" <nicolas.ferre@atmel.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"soren.brinkmann@xilinx.com" <soren.brinkmann@xilinx.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/1] net/macb: add TX multiqueue support for gem
Date: Fri, 12 Dec 2014 10:52:12 +0100 [thread overview]
Message-ID: <20141212105212.3b9c5810@free-electrons.com> (raw)
In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6D1CA0BA36@AcuExch.aculab.com>
Dear David Laight,
On Fri, 12 Dec 2014 09:45:30 +0000, David Laight wrote:
> From: Thomas Petazzoni
> > On Thu, 11 Dec 2014 11:16:51 +0100, Cyrille Pitchen wrote:
> >
> > > +#define GEM_ISR1 0x0400
> > > +#define GEM_ISR2 0x0404
> > > +#define GEM_ISR3 0x0408
> > > +#define GEM_ISR4 0x040c
> > > +#define GEM_ISR5 0x0410
> > > +#define GEM_ISR6 0x0414
> > > +#define GEM_ISR7 0x0418
> >
> > What about doing instead:
> >
> > #define GEM_ISR(q) ((q) == 0 ? MACB_ISR : 0x400 + (q) << 2)
> >
> > And ditto for all other registers, which will save a lot of boring repeated code.
>
> It will probably add a lot of object code and, depending on how often
> the registers are accesses, might have performance impact.
>
> Having:
> #define GEM_ISR(n) (0x400 + (n) << 4)
> will save source code.
Except that this won't work for n == 0, because for n == 0, the
register offset is not 0x400.
And in fact, my code was also wrong, it should be:
((q) == 0 ? MACB_ISR : 0x400 + ((q)-1) << 2))
Since q=1 is at 0x400.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
prev parent reply other threads:[~2014-12-12 9:52 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-11 10:16 [PATCH v2 0/1] " Cyrille Pitchen
2014-12-11 10:16 ` [PATCH v2 1/1] " Cyrille Pitchen
2014-12-11 19:31 ` Thomas Petazzoni
2014-12-12 8:24 ` Cyrille Pitchen
2014-12-12 9:45 ` David Laight
2014-12-12 8:59 ` Cyrille Pitchen
2014-12-12 9:59 ` David Laight
2014-12-12 9:57 ` Cyrille Pitchen
2014-12-12 9:52 ` Thomas Petazzoni [this message]
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