From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753368AbbBXQbn (ORCPT ); Tue, 24 Feb 2015 11:31:43 -0500 Received: from pmta2.delivery1.ore.mailhop.org ([54.149.155.156]:53119 "EHLO pmta2.delivery1.ore.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753084AbbBXQbf (ORCPT ); Tue, 24 Feb 2015 11:31:35 -0500 X-Mail-Handler: DuoCircle Outbound SMTP X-Originating-IP: 104.193.169.186 X-Report-Abuse-To: abuse@duocircle.com (see https://support.duocircle.com/support/solutions/articles/5000540958-duocircle-standard-smtp-abuse-information for abuse reporting information) X-MHO-User: U2FsdGVkX19jE2YeXht4UgtrW6saAmlk Date: Tue, 24 Feb 2015 08:27:20 -0800 From: Tony Lindgren To: Ravikumar Kattekola , Tero Kristo Cc: bcousson@baylibre.com, mark.rutland@arm.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes Message-ID: <20150224162719.GA28244@atomide.com> References: <1422724005-9415-1-git-send-email-rk@ti.com> <54E5FC6D.7040701@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <54E5FC6D.7040701@ti.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Ravikumar Kattekola [150219 08:13]: > On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote: > >Fix bypass clock source for a few DPLLs. > > > >On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected > >to a mux and the output from mux is routed to the bypass clkout. > >Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents. > > > >Tested against: > > tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git > > branch: master > >On: > >CPU : OMAP5432 ES2.0 > >Board: OMAP5432 uEVM > >and > >CPU : DRA752 ES1.0 > >Board: DRA7xx > > > > > >Ravikumar Kattekola (2): > > ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others > > ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others > > > > arch/arm/boot/dts/dra7xx-clocks.dtsi | 90 ++++++++++++++++++++++++++++---- > > arch/arm/boot/dts/omap54xx-clocks.dtsi | 41 +++++++++++++-- > > 2 files changed, 118 insertions(+), 13 deletions(-) > > > Hi Benoit, > Can these fixes be looked into for 3.20-rc? Seem like valid fixes to me. Tero, care to take a look at these and ack if OK? Regards, Tony