From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756153AbbCBRYn (ORCPT ); Mon, 2 Mar 2015 12:24:43 -0500 Received: from foss.arm.com ([217.140.101.70]:48048 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754235AbbCBRYm (ORCPT ); Mon, 2 Mar 2015 12:24:42 -0500 Date: Mon, 2 Mar 2015 17:24:44 +0000 From: Will Deacon To: Baptiste Reynal Cc: "iommu@lists.linux-foundation.org" , "kvmarm@lists.cs.columbia.edu" , "tech@virtualopensystems.com" , Joerg Roedel , "moderated list:ARM SMMU DRIVER" , open list Subject: Re: [PATCH 1/1] iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS condition Message-ID: <20150302172444.GB7919@arm.com> References: <1425315442-29584-1-git-send-email-b.reynal@virtualopensystems.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1425315442-29584-1-git-send-email-b.reynal@virtualopensystems.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 02, 2015 at 04:57:22PM +0000, Baptiste Reynal wrote: > This patch is a fix to "iommu/arm-smmu: add support for iova_to_phys > through ATS1PR". > According to ARM documentation, translation registers are optional even > in SMMUv1, so ID0_S1TS needs to be checked to verify their presence. > > Signed-off-by: Baptiste Reynal > --- > drivers/iommu/arm-smmu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index fc13dd5..d4beca4 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -1556,7 +1556,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) > return -ENODEV; > } > > - if (smmu->version == 1 || (!(id & ID0_ATOSNS) && (id & ID0_S1TS))) { > + if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) { > smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; > dev_notice(smmu->dev, "\taddress translation ops\n"); I'm not sure this is a complete fix. Shouldn't we also check that the domain is a stage-1 domain in arm_smmu_iova_to_phys? (potential fixup below). Will --->8 diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index fc13dd56953e..107163295cbc 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1288,12 +1288,15 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, return 0; spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); - if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS) + + if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS && + smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { ret = arm_smmu_iova_to_phys_hard(domain, iova); - else + } else { ret = ops->iova_to_phys(ops, iova); - spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); + } + spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); return ret; }