From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754104AbbCBSmJ (ORCPT ); Mon, 2 Mar 2015 13:42:09 -0500 Received: from skprod2.natinst.com ([130.164.80.23]:58368 "EHLO ni.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751526AbbCBSmI (ORCPT ); Mon, 2 Mar 2015 13:42:08 -0500 Date: Mon, 2 Mar 2015 12:41:34 -0600 From: Josh Cartwright To: Kedareswara rao Appana Cc: dan.j.williams@intel.com, vinod.koul@intel.com, michal.simek@xilinx.com, soren.brinkmann@xilinx.com, svemula@xilinx.com, linux-kernel@vger.kernel.org, Srikanth Thokala , anirudh@xilinx.com, dmaengine@vger.kernel.org, appanad@xilinx.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5] dma: Add Xilinx AXI Direct Memory Access Engine driver support Message-ID: <20150302184134.GC681@jcartwri.amer.corp.natinst.com> References: <6f3b34935c0f405199cacd5312e972ac@BN1BFFO11FD017.protection.gbl> MIME-Version: 1.0 In-Reply-To: <6f3b34935c0f405199cacd5312e972ac@BN1BFFO11FD017.protection.gbl> User-Agent: Mutt/1.5.23 (2014-03-12) X-MIMETrack: Itemize by SMTP Server on US-AUS-MGWOut2/AUS/H/NIC(Release 8.5.3FP6|November 21, 2013) at 03/02/2015 12:41:34 PM, Serialize by Router on US-AUS-MGWOut2/AUS/H/NIC(Release 8.5.3FP6|November 21, 2013) at 03/02/2015 12:41:42 PM, Serialize complete at 03/02/2015 12:41:42 PM Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2015-03-02_01:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello! I looked through your driver and have some comments. On Mon, Mar 02, 2015 at 11:25:11PM +0530, Kedareswara rao Appana wrote: > This is the driver for the AXI Direct Memory Access (AXI DMA) > core, which is a soft Xilinx IP core that provides high- > bandwidth direct memory access between memory and AXI4-Stream > type target peripherals. > > Signed-off-by: Srikanth Thokala > Signed-off-by: Kedareswara rao Appana [..] > +++ b/drivers/dma/Kconfig > @@ -425,6 +425,19 @@ config IMG_MDC_DMA > help > Enable support for the IMG multi-threaded DMA controller (MDC). > > +config XILINX_DMA > + tristate "Xilinx AXI DMA Engine" > + depends on (ARCH_ZYNQ || MICROBLAZE) Why do you need this dependency? I'm assuming this IP has usefulness outside of microblaze and Zynq. > + select DMA_ENGINE > + help > + Enable support for Xilinx AXI DMA Soft IP. > + > + This engine provides high-bandwidth direct memory access > + between memory and AXI4-Stream type target peripherals. > + It has two stream interfaces/channels, Memory Mapped to > + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the > + data transfers. Odd indention here. At least indent this paragraph like the sentence above. [..] > +++ b/drivers/dma/xilinx/xilinx_dma.c [..] > +/** > + * xilinx_dma_halt - Halt DMA channel > + * @chan: Driver specific DMA channel > + */ > +static void xilinx_dma_halt(struct xilinx_dma_chan *chan) > +{ > + int loop = XILINX_DMA_LOOP_COUNT; > + > + dma_ctrl_clr(chan, XILINX_DMA_REG_CONTROL, > + XILINX_DMA_CR_RUNSTOP_MASK); > + > + /* Wait for the hardware to halt */ > + do { > + if (dma_ctrl_read(chan, XILINX_DMA_REG_STATUS) & > + XILINX_DMA_SR_HALTED_MASK) > + break; > + } while (loop--); > + > + if (!loop) { Looks like a very subtle off-by-one error here. (And elsewhere you use this pattern). Josh