From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933202AbbCQQi3 (ORCPT ); Tue, 17 Mar 2015 12:38:29 -0400 Received: from bombadil.infradead.org ([198.137.202.9]:58648 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932071AbbCQQi0 (ORCPT ); Tue, 17 Mar 2015 12:38:26 -0400 Date: Tue, 17 Mar 2015 17:37:56 +0100 From: Peter Zijlstra To: Mathieu Desnoyers Cc: linux-kernel@vger.kernel.org, KOSAKI Motohiro , Steven Rostedt , "Paul E. McKenney" , Nicholas Miell , Linus Torvalds , Ingo Molnar , Alan Cox , Lai Jiangshan , Stephen Hemminger , Andrew Morton , Josh Triplett , Thomas Gleixner , David Howells Subject: Re: [RFC PATCH] sys_membarrier(): system/process-wide memory barrier (x86) (v12) Message-ID: <20150317163756.GE23123@twins.programming.kicks-ass.net> References: <1426447459-28620-1-git-send-email-mathieu.desnoyers@efficios.com> <20150316141939.GE21418@twins.programming.kicks-ass.net> <1203077851.9491.1426520636551.JavaMail.zimbra@efficios.com> <20150316172104.GH21418@twins.programming.kicks-ass.net> <1003922584.10662.1426532015839.JavaMail.zimbra@efficios.com> <20150316205435.GJ21418@twins.programming.kicks-ass.net> <910572156.13900.1426556725438.JavaMail.zimbra@efficios.com> <20150317063059.GJ2896@worktop.programming.kicks-ass.net> <680573370.19261.1426598016060.JavaMail.zimbra@efficios.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <680573370.19261.1426598016060.JavaMail.zimbra@efficios.com> User-Agent: Mutt/1.5.21 (2012-12-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 17, 2015 at 01:13:36PM +0000, Mathieu Desnoyers wrote: > > Its basically: WMB + ACQUIRE, which theoretically can leak a read in, > > but nobody sane _delays_ reads, you want to speculate reads, not > > postpone. > > If I believe the memory ordering table at > https://en.wikipedia.org/wiki/Memory_ordering , there appears > to be quite a few architectures that can reorder loads after loads, > and loads after stores: Alpha, ARMv7, PA-RISC, SPARC RMO, x86 oostore > and ia64. There may be subtle details that would allow us to > do without the barriers in specific situations, but for that I'd > very much like to hear what Paul has to say. So I was starting to write that you can get load after load by one speculating more than the other, but I suppose you can delay loads just fine too. Imagine getting a cache miss on a load, the OoO engine can then continue execution until it hits a hard dependency, so you're effectively delaying the load. So yeah, if we want to be able to replace smp_rmb() with a barrier+sys_membar() we need to promote the smp_mb__before_spinlock() to smp_mb__after_unlock_lock() or so, that would only penalize PPC a bit.