From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755821AbbCSBgY (ORCPT ); Wed, 18 Mar 2015 21:36:24 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:60740 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755646AbbCSBgV (ORCPT ); Wed, 18 Mar 2015 21:36:21 -0400 Date: Thu, 19 Mar 2015 10:36:18 +0900 From: Simon Horman To: Geert Uytterhoeven Cc: Thomas Gleixner , Jason Cooper , Magnus Damm , linux-sh@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/7] irqchip: renesas-irqc: Add more register documentation Message-ID: <20150319013617.GG14051@verge.net.au> References: <1426704961-27322-1-git-send-email-geert+renesas@glider.be> <1426704961-27322-2-git-send-email-geert+renesas@glider.be> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1426704961-27322-2-git-send-email-geert+renesas@glider.be> Organisation: Horms Solutions Ltd. User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 18, 2015 at 07:55:55PM +0100, Geert Uytterhoeven wrote: > Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman > --- > drivers/irqchip/irq-renesas-irqc.c | 20 +++++++++++++++----- > 1 file changed, 15 insertions(+), 5 deletions(-) > > diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c > index 2ea3412fdf8cc668..2ce2edf8ec8ec182 100644 > --- a/drivers/irqchip/irq-renesas-irqc.c > +++ b/drivers/irqchip/irq-renesas-irqc.c > @@ -30,14 +30,24 @@ > #include > #include > > -#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */ > +#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */ > > -#define IRQC_REQ_STS 0x00 > -#define IRQC_EN_STS 0x04 > -#define IRQC_EN_SET 0x08 > +#define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */ > +#define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */ > +#define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */ > #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10)) > -#define DETECT_STATUS 0x100 > + /* SYS-CPU vs. RT-CPU */ > +#define DETECT_STATUS 0x100 /* IRQn Detect Status Register */ > +#define MONITOR 0x104 /* IRQn Signal Level Monitor Register */ > +#define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */ > +#define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */ > +#define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */ > +#define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */ > +#define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */ > +#define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */ > +#define CHTEN_STS 0x120 /* Chattering Reduction Status Register */ > #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04)) > + /* IRQn Configuration Register */ > > struct irqc_irq { > int hw_irq; > -- > 1.9.1 >