From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752739AbbC2Ujb (ORCPT ); Sun, 29 Mar 2015 16:39:31 -0400 Received: from si-002-i39.relay.mailchannels.net ([184.154.112.204]:49384 "EHLO relay.mailchannels.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752418AbbC2Uj3 (ORCPT ); Sun, 29 Mar 2015 16:39:29 -0400 X-Sender-Id: duocircle|x-authuser|jac299792458 X-Sender-Id: duocircle|x-authuser|jac299792458 X-MC-Relay: Neutral X-MailChannels-SenderId: duocircle|x-authuser|jac299792458 X-MailChannels-Auth-Id: duocircle X-MC-Loop-Signature: 1427661567019:692541782 X-MC-Ingress-Time: 1427661567019 X-Mail-Handler: DuoCircle Outbound SMTP X-Originating-IP: 72.84.113.125 X-Report-Abuse-To: abuse@duocircle.com (see https://support.duocircle.com/support/solutions/articles/5000540958-duocircle-standard-smtp-abuse-information for abuse reporting information) X-MHO-User: U2FsdGVkX18U6A7dw97Q80n+vVN00/Wr9NHu7LoHgs4= X-DKIM: OpenDKIM Filter v2.6.8 io D0899805AF Date: Sun, 29 Mar 2015 20:39:23 +0000 From: Jason Cooper To: Markos Chandras Cc: linux-mips@linux-mips.org, Thomas Gleixner , Andrew Bresticker , Qais Yousef , linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/3] irqchip: irq-mips-gic: Add new functions to start/stop the GIC counter Message-ID: <20150329203923.GF25778@io.lakedaemon.net> References: <1427113923-9840-1-git-send-email-markos.chandras@imgtec.com> <1427113923-9840-2-git-send-email-markos.chandras@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1427113923-9840-2-git-send-email-markos.chandras@imgtec.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-AuthUser: jac299792458 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 23, 2015 at 12:32:01PM +0000, Markos Chandras wrote: > We add new functions to start and stop the GIC counter since there are no > guarantees the counter will be running after a CPU reset. The GIC counter > is stopped by setting the 29th bit on the GIC Config register and it is > started by clearing that bit. > > Cc: Thomas Gleixner > Cc: Jason Cooper > Cc: Andrew Bresticker > Cc: Qais Yousef > Cc: > Signed-off-by: Markos Chandras > --- > drivers/irqchip/irq-mips-gic.c | 21 +++++++++++++++++++++ > include/linux/irqchip/mips-gic.h | 2 ++ > 2 files changed, 23 insertions(+) Applied to irqchip/core thx, Jason.