From: Peter Zijlstra <peterz@infradead.org>
To: Kan Liang <kan.liang@intel.com>
Cc: linux-kernel@vger.kernel.org, mingo@kernel.org,
acme@infradead.org, eranian@google.com, andi@firstfloor.org
Subject: Re: [PATCH V5 5/6] perf, x86: drain PEBS buffer during context switch
Date: Mon, 30 Mar 2015 15:50:45 +0200 [thread overview]
Message-ID: <20150330135045.GW23123@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1424701556-28270-6-git-send-email-kan.liang@intel.com>
On Mon, Feb 23, 2015 at 09:25:55AM -0500, Kan Liang wrote:
> From: Yan, Zheng <zheng.z.yan@intel.com>
>
> Flush the PEBS buffer during context switch if PEBS interrupt threshold
> is larger than one. This allows perf to supply TID for sample outputs.
>
> Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
> Signed-off-by: Kan Liang <kan.liang@intel.com>
> ---
> arch/x86/kernel/cpu/perf_event.h | 3 +++
> arch/x86/kernel/cpu/perf_event_intel.c | 11 +++++++++-
> arch/x86/kernel/cpu/perf_event_intel_ds.c | 33 ++++++++++++++++++++++++++++--
> arch/x86/kernel/cpu/perf_event_intel_lbr.c | 3 ---
> 4 files changed, 44 insertions(+), 6 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
> index bc4ae3b..b4f6431 100644
> --- a/arch/x86/kernel/cpu/perf_event.h
> +++ b/arch/x86/kernel/cpu/perf_event.h
> @@ -151,6 +151,7 @@ struct cpu_hw_events {
> */
> struct debug_store *ds;
> u64 pebs_enabled;
> + bool pebs_sched_cb_enabled;
>
> /*
> * Intel LBR bits
Why do we need that extra state? I would've expected to see a inc/dec
for every AUTO_RELOAD that gets added/removed.
> @@ -704,13 +717,20 @@ void intel_pmu_pebs_enable(struct perf_event *event)
> * When the event is constrained enough we can use a larger
> * threshold and run the event with less frequent PMI.
> */
> - if (0 && /* disable this temporarily */
> - (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) &&
> + if ((hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) &&
> !(event->attr.sample_type & ~PEBS_FREERUNNING_FLAGS)) {
> threshold = ds->pebs_absolute_maximum -
> x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
> + if (first_pebs) {
> + perf_sched_cb_inc(event->ctx->pmu);
> + cpuc->pebs_sched_cb_enabled = true;
> + }
> } else {
> threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
> + if (cpuc->pebs_sched_cb_enabled) {
> + perf_sched_cb_dec(event->ctx->pmu);
> + cpuc->pebs_sched_cb_enabled = false;
> + }
> }
> if (first_pebs || ds->pebs_interrupt_threshold > threshold)
> ds->pebs_interrupt_threshold = threshold;
I'm confused, why do you do sched_cb_dec for every event that wasn't
AUTO_RELOAD?
next prev parent reply other threads:[~2015-03-30 13:50 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-23 14:25 [PATCH V5 0/6] large PEBS interrupt threshold Kan Liang
2015-02-23 14:25 ` [PATCH V5 1/6] perf, x86: use the PEBS auto reload mechanism when possible Kan Liang
2015-03-30 12:06 ` Peter Zijlstra
2015-03-30 14:02 ` Peter Zijlstra
2015-02-23 14:25 ` [PATCH V5 2/6] perf, x86: introduce setup_pebs_sample_data() Kan Liang
2015-02-23 14:25 ` [PATCH V5 3/6] perf, x86: large PEBS interrupt threshold Kan Liang
2015-03-02 17:08 ` Stephane Eranian
2015-03-02 17:59 ` Andi Kleen
2015-03-02 18:07 ` Stephane Eranian
2015-03-30 13:54 ` Peter Zijlstra
2015-02-23 14:25 ` [PATCH V5 4/6] perf, x86: handle multiple records in PEBS buffer Kan Liang
2015-03-30 13:45 ` Peter Zijlstra
2015-03-30 17:19 ` Liang, Kan
2015-03-30 17:25 ` Andi Kleen
2015-03-30 17:43 ` Liang, Kan
2015-03-30 17:45 ` Andi Kleen
2015-03-30 20:07 ` Peter Zijlstra
2015-03-30 20:11 ` Andi Kleen
2015-03-30 21:24 ` Peter Zijlstra
2015-03-30 21:53 ` Andi Kleen
2015-02-23 14:25 ` [PATCH V5 5/6] perf, x86: drain PEBS buffer during context switch Kan Liang
2015-03-30 13:50 ` Peter Zijlstra [this message]
2015-02-23 14:25 ` [PATCH V5 6/6] perf, x86: enlarge PEBS buffer Kan Liang
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