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From: Catalin Marinas <catalin.marinas@arm.com>
To: Dirk Behme <dirk.behme@de.bosch.com>
Cc: "Michal Simek" <michal.simek@xilinx.com>,
	linux-arm-kernel@lists.infradead.org,
	"Josh Cartwright" <josh.cartwright@ni.com>,
	"Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
	"Russell King" <linux@arm.linux.org.uk>,
	monstr@monstr.eu, linux-kernel@vger.kernel.org,
	"Thomas Betker" <thomas.betker@rohde-schwarz.com>,
	"Steffen Trumtrar" <s.trumtrar@pengutronix.de>,
	"Sören Brinkmann" <soren.brinkmann@xilinx.com>
Subject: Re: [PATCH] ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1)
Date: Thu, 14 May 2015 17:40:49 +0100	[thread overview]
Message-ID: <20150514164048.GF19345@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <55519E47.7040008@de.bosch.com>

On Tue, May 12, 2015 at 08:31:35AM +0200, Dirk Behme wrote:
> On 12.05.2015 08:22, Michal Simek wrote:
> >From: Thomas Betker <thomas.betker@rohde-schwarz.com>
> >
> >This patch is based on the
> >commit 1a8e41cd672f ("ARM: 6395/1: VExpress: Set bit 22 in the PL310
> >(cache controller) AuxCtlr register")
> 
> I've been under the impression that this shouldn't be done in the kernel,
> but in the boot loader/firmware:
> 
> https://lkml.org/lkml/2015/2/20/199
> 
> http://lists.denx.de/pipermail/u-boot/2015-March/207803.html

If you can fix it in the boot loader or firmware even better. If it's
not doable, this patch will help (if Russell takes it):

http://article.gmane.org/gmane.linux.ports.sh.devel/45685

-- 
Catalin

  parent reply	other threads:[~2015-05-14 16:40 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-12  6:22 Michal Simek
2015-05-12  6:31 ` Dirk Behme
2015-05-12  6:50   ` Michal Simek
2015-05-12 12:42     ` Thomas.Betker
2015-05-14 16:40   ` Catalin Marinas [this message]
2015-05-18  8:31     ` Thomas.Betker
2015-05-12 15:12 ` Josh Cartwright

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