From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755848AbbE2Jtz (ORCPT ); Fri, 29 May 2015 05:49:55 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:33523 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755815AbbE2Jtq (ORCPT ); Fri, 29 May 2015 05:49:46 -0400 Date: Fri, 29 May 2015 10:49:41 +0100 From: Mark Brown To: Laxman Dewangan Cc: lgirdwood@gmail.com, linux-kernel@vger.kernel.org, cfreeman@nvidia.com, abrestic@chromium.org, afrid@nvidia.com Message-ID: <20150529094941.GL21577@sirena.org.uk> References: <1432737621-27590-1-git-send-email-ldewangan@nvidia.com> <20150528135245.GU21577@sirena.org.uk> <5567FE68.5070006@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="0sZ5QJxrrCULd7z4" Content-Disposition: inline In-Reply-To: <5567FE68.5070006@nvidia.com> X-Cookie: Positively no smoking. User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: 94.175.94.161 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH 1/2] regulator: core: add support to get VSEL register from hw driver X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --0sZ5QJxrrCULd7z4 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, May 29, 2015 at 11:21:36AM +0530, Laxman Dewangan wrote: > In our system, CPU-DFLL is another HW module which controls the CPU voltage > based on CPU frequency request. It issues the i2c command to the device for > voltage change when frequency get change. For this reason, CPU-DFLL need the > VSEL register address. The CPU DVFS SW driver controls the DVS input pin to > control sleep entry/exit and VOUT0 for voltage change. So on this case, we > really donot need to change the VSEL register address for active state > voltage change and use the DVS for sleep entry/exit. Sure, that's the normal use case for this stuff. > The problem will be there when external controller use the DVS pin for DVFS > and need two register address here. In this case, I think external > controller need to get information from different mechanism rather than via > regulator driver to avoid complication on regulator driver/framework. Probably, it's definitely getting complicated (though in this case where we only need one register we ought to be more able to manage it, not that I have bright ideas right now). --0sZ5QJxrrCULd7z4 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJVaDY0AAoJECTWi3JdVIfQPwQH/1ujSUveAy0OPHtl0uwbwuGt OxGfIH30R0CGtWHZ/qrcHUNy2DvWNs7SO8EsJk+7HKyKRjzdtn1UqJXtnT3oDIrX xm9q2d2u2+MFKo4j+XeqIg8Q4dsELvcgTF6fBSltY+9LYsc9hMBdYqgKsSO7hvgO 8SF3zOllW/kNhs4hItdm4gP4yuQiGmITfAQW7GZgn7ja8E8LT5fmaO3czuOxEQX1 x+6IU5RKWdZnN+VrVgcxiOz2lmJTuiUICGkqqg1XhgR/nYvp+gxbbArtE0YXLTZh kQI10UcAKaa0o4FfqLpLnVZRy7HfuFrNCE1klRAcpujPXE2jvRKUMGQoF+4vzoI= =ngO3 -----END PGP SIGNATURE----- --0sZ5QJxrrCULd7z4--