From: Mark Brown <broonie@kernel.org>
To: Murali Karicheri <m-karicheri2@ti.com>
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] spi: davinci: change the lower limit of pre-scale divider to 1
Date: Wed, 10 Jun 2015 18:28:18 +0100 [thread overview]
Message-ID: <20150610172818.GG14071@sirena.org.uk> (raw)
In-Reply-To: <1433921022-13151-1-git-send-email-m-karicheri2@ti.com>
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On Wed, Jun 10, 2015 at 03:23:42AM -0400, Murali Karicheri wrote:
> SPI hardware spec for Keystone specify a lower value of 0 for pre-scale
> divider which determine what max value of spi clock (spi-max-frequency)
> the device can support. This translates to a clock divider of 2. So fix
> the lower limit value used for the boundary check in
> davinci_spi_get_prescale() function to 1 so that a maximum of spi device
> clock rate / 2 is possible to be set for spi-max-frequency.
Applied, thanks.
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prev parent reply other threads:[~2015-06-10 17:28 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-10 7:23 Murali Karicheri
2015-06-10 17:28 ` Mark Brown [this message]
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