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Date: Wed, 24 Jun 2015 14:56:17 +0300
From: Roger Quadros <rogerq@ti.com>
To: Roger Quadros <rogerq@ti.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>, <bcousson@baylibre.com>,
        <tony@atomide.com>, <balbi@ti.com>, <devicetree@vger.kernel.org>,
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        <nsekhar@ti.com>
Subject: Re: [PATCH 08/17] ARM: dts: dra7: Add dt node for the sycon pcie
Message-ID: <20150624145617.e5248d466fe5b2e0eb1ca087@ti.com>
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On Wed, 24 Jun 2015 14:50:17 +0300
Roger Quadros <rogerq@ti.com> wrote:

> On Tue, 23 Jun 2015 17:28:53 +0530
> Kishon Vijay Abraham I <kishon@ti.com> wrote:
> 
> > Add new device tree node for the control module register space where
> > PCIe registers are present.
> > 
> > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> > ---
> >  arch/arm/boot/dts/dra7.dtsi |    5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> > index 260f300..3f434f7 100644
> > --- a/arch/arm/boot/dts/dra7.dtsi
> > +++ b/arch/arm/boot/dts/dra7.dtsi
> > @@ -291,6 +291,11 @@
> >  			reg = <0x4a002e00 0x7c>;
> >  		};
> >  
> > +		dra7_ctrl_pcie: tisyscon@4a003c00 {
> > +			compatible = "syscon";
> > +			reg = <0x4a003c00 0x48>;
> > +		};
> > +
> 
> Why do you need to start from 0x4a003c00?
> CTRL_CORE_PCIESS1_PCS1 is at 0x4a003c24

Also, why can't this dra7_ctrl_pcie node be where scm_conf is.

> 
> >  		sdma: dma-controller@4a056000 {
> >  			compatible = "ti,omap4430-sdma";
> >  			reg = <0x4a056000 0x1000>;
> > -- 
> > 1.7.9.5
> > 
> 
> cheers,
> -roger
> --
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