From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754924AbbGFTJ2 (ORCPT ); Mon, 6 Jul 2015 15:09:28 -0400 Received: from bombadil.infradead.org ([198.137.202.9]:44610 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751726AbbGFTJ0 (ORCPT ); Mon, 6 Jul 2015 15:09:26 -0400 Date: Mon, 6 Jul 2015 21:09:17 +0200 From: Peter Zijlstra To: linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, mahesh.kumar.p@intel.com, tglx@linutronix.de, rafael.j.wysocki@intel.com, andriy.shevchenko@linux.intel.com, hpa@zytor.com, mingo@kernel.org, aubrey.li@linux.intel.com Cc: linux-tip-commits@vger.kernel.org Subject: Re: [tip:x86/platform] x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface Message-ID: <20150706190917.GK3644@twins.programming.kicks-ass.net> References: <1436192944-56496-5-git-send-email-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2012-12-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jul 06, 2015 at 09:35:33AM -0700, tip-bot for Kumar P Mahesh wrote: > Commit-ID: daf61e1b7fc31d553fe3bf2dead95d9404ad0f57 > Gitweb: http://git.kernel.org/tip/daf61e1b7fc31d553fe3bf2dead95d9404ad0f57 > Author: Kumar P Mahesh > AuthorDate: Mon, 6 Jul 2015 17:29:03 +0300 > Committer: Ingo Molnar > CommitDate: Mon, 6 Jul 2015 17:50:59 +0200 > > x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface > > The patch adds CHT PMC interface. This exposes all the South IP > device power states and S0ix states for CHT. The bit map of > FUNC_DIS and D3_STS_0 registers for SoCs are consistent. The > D3_STS_1 and FUNC_DIS_2 registers, however, are not aligned. > This is fixed by splitting a common mapping on per register basis. TLA collision.. I thought this was about performance monitor counters :/