From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753790AbbHFXZs (ORCPT ); Thu, 6 Aug 2015 19:25:48 -0400 Received: from gate.crashing.org ([63.228.1.57]:59837 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752210AbbHFXZr (ORCPT ); Thu, 6 Aug 2015 19:25:47 -0400 Date: Thu, 6 Aug 2015 18:25:06 -0500 From: Segher Boessenkool To: Scott Wood Cc: Christophe Leroy , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/2] powerpc32: optimise csum_partial() loop Message-ID: <20150806232506.GB22196@gate.crashing.org> References: <67cf476f657e87b2ea586951a57ae3ba3c1e3c0c.1435655733.git.christophe.leroy@c-s.fr> <20150806003059.GD18479@gate.crashing.org> <1438828301.2097.126.camel@freescale.com> <20150806043938.GE18479@gate.crashing.org> <1438901145.2097.170.camel@freescale.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1438901145.2097.170.camel@freescale.com> User-Agent: Mutt/1.4.2.3i Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 06, 2015 at 05:45:45PM -0500, Scott Wood wrote: > > The original loop was already optimal, as the comment said. > > The comment says that bdnz has zero overhead. That doesn't mean the adde > won't stall waiting for the load result. adde is execution serialising on those cores; it *always* stalls, that is, it won't run until it is next to complete. > > The new code adds extra instructions and a mispredicted branch. > > Outside the main loop. Sure, I never said it was super-bad or anything. > > You also might get less overlap between the loads and adde (I didn't check > > if there is any originally): those instructions are no longer > > interleaved. > > > > I think it is a stupid idea to optimise code for all 32-bit PowerPC > > CPUs based on solely what is best for a particularly simple, slow > > implementation; and that is what this patch is doing. > > The simple and slow implementation is the one that needs optimizations the > most. And, on the other hand, optimising for atypical (mostly) in-order single-issue chips without branch folding, hurts performance on other chips the most. Well, dual-issue in-order might be worse :-P > If this makes performance non-negligibly worse on other 32-bit chips, and is > an important improvement on 8xx, then we can use an ifdef since 8xx already > requires its own kernel build. I'd prefer to see a benchmark showing that it > actually does make things worse on those chips, though. And I'd like to see a benchmark that shows it *does not* hurt performance on most chips, and does improve things on 8xx, and by how much. But it isn't *me* who has to show that, it is not my patch. If these csum routines actually matter for performance that much, there really *should* be chip-specific implementations. Segher