From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753327AbbIGRch (ORCPT ); Mon, 7 Sep 2015 13:32:37 -0400 Received: from mail-bn1on0096.outbound.protection.outlook.com ([157.56.110.96]:11728 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752397AbbIGRce (ORCPT ); Mon, 7 Sep 2015 13:32:34 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Robert.Richter@caviumnetworks.com; Date: Mon, 7 Sep 2015 19:32:18 +0200 From: Robert Richter To: Marc Zyngier CC: "Suzuki K. Poulose" , Robert Richter , Thomas Gleixner , Jason Cooper , Catalin Marinas , Will Deacon , Tirumalesh Chalamarla , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v4 2/5] irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154 Message-ID: <20150907173218.GV1820@rric.localdomain> References: <1439576885-15621-1-git-send-email-rric@kernel.org> <1439576885-15621-3-git-send-email-rric@kernel.org> <55EDC12E.8000408@arm.com> <55EDC4DC.4040405@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <55EDC4DC.4040405@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-Originating-IP: [92.224.193.81] X-ClientProxiedBy: AM3PR01CA042.eurprd01.prod.exchangelabs.com (10.141.191.32) To BY1PR0701MB1612.namprd07.prod.outlook.com (25.162.110.153) X-Microsoft-Exchange-Diagnostics: 1;BY1PR0701MB1612;2:7YoE9zHx6pKotHxIcYFFaca4oPIKqgk9PQ70rFN+/+s5a31S2W0hBI4zAcf/3J9eBmYJK/A0r4lNLde83Hhata96R5gLMjhlXFqX+Mnofkc0qgU5s9fsDoDG6FGPBjKEPlIoJ7mKqeBUstU9KwW3nZyUcIgLBDtu/GxSmFMDB60=;3:TbXdA4jB9i7W/O9xxnFG4wEeTOW36Aj13NMZ8PM1aG8MvC9phXQ/BeQeX6u/gN7A0PRjxuI76ojuc6AOVLhGYMpkN1GGG3DG3S7pw5IT3IB6QR6V3gLSZgUZf2bVdVAkQtiwtC/9LUJyss70N6n+rQ==;25:YlJVll2/tfIiNkwoNoGKNkbMB26OglLldf4LabII4hSWw2lTWcGNNbR4iCDxCUs2py29iuHRN/7vZcX0sru7soFWfH9/sqSaNjBIWVCQXi25OdEqtIhA1OEQZz7y97WsodS4/zXjuZedw9HQlLqxqO4I71K8QHdkSopYQQV07mUTj5916MlclSDvG0BxX4x2rpqlr5R70+3X7YuWHU41PYrbZvV05IouYFqYnNxNEDmFloUN1thB00AZQjhYr61hND5xMggccfLtv0oRnahU4g== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR0701MB1612; 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Poulose wrote: > > On 14/08/15 19:28, Robert Richter wrote: > >> From: Robert Richter > >> +static void gicv3_enable_quirks(void) > >> +{ > >> + if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) > >> + static_key_slow_inc(&is_cavium_thunderx); > > > > May be you could use the enable() method added to struct arm64_cpu_capability > > here to perform the above operation, added by James : > > > > commit 1c0763037f1e1caef739e36e09c6d41ed7b61b2d > > Author: James Morse > > Date: Tue Jul 21 13:23:28 2015 +0100 > > > > arm64: kernel: Add cpufeature 'enable' callback > > > > > >> +} > >> + > >> static int __init gic_of_init(struct device_node *node, struct device_node *parent) > >> { > >> void __iomem *dist_base; > >> @@ -825,6 +863,8 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare > >> gic_data.nr_redist_regions = nr_redist_regions; > >> gic_data.redist_stride = redist_stride; > >> > >> + gicv3_enable_quirks(); > >> + > > > > than adding a hook here ? > > It feels like a good idea, except that it creates a weird dependency > between the core arch code and the GIC driver. Can you think of an > elegant way to deal with this? The only chance I see is to move it all to the driver and adding enable() calls to the caps in gicv3_errata: static void gicv3_enable_quirks(void) { check_cpu_capabilities(gicv3_errata, "enabling workaround for"); } Here the code is kept in the driver and called during driver init. But current solution looks more elegant and simpler to me. So I would not change it. -Robert