From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754135AbbIPRu4 (ORCPT ); Wed, 16 Sep 2015 13:50:56 -0400 Received: from mga09.intel.com ([134.134.136.24]:31910 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752826AbbIPRuw (ORCPT ); Wed, 16 Sep 2015 13:50:52 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,540,1437462000"; d="scan'208";a="646120083" Subject: [PATCH 01/26] x86, fpu: add placeholder for Processor Trace XSAVE state To: dave@sr71.net Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org From: Dave Hansen Date: Wed, 16 Sep 2015 10:49:04 -0700 References: <20150916174903.E112E464@viggo.jf.intel.com> In-Reply-To: <20150916174903.E112E464@viggo.jf.intel.com> Message-Id: <20150916174904.E002DB09@viggo.jf.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is an XSAVE state component for Intel Processor Trace. But, we do not use it and do not expect to ever use it. We add a placeholder in the code for it so it is not a mystery and also so we do not need an explicit enum initialization for Protection Keys in a moment. Why will we never use it? According to Andi Kleen: The XSAVE support assumes that there is a single buffer for each thread. But perf generally doesn't work this way, it usually has only a single perf event per CPU per user, and when tracing multiple threads on that CPU it inherits perf event buffers between different threads. So XSAVE per thread cannot handle this inheritance case directly. Using multiple XSAVE areas (another one per perf event) would defeat some of the state caching that the CPUs do. --- b/arch/x86/include/asm/fpu/types.h | 1 + b/arch/x86/kernel/fpu/xstate.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff -puN arch/x86/include/asm/fpu/types.h~pt-xstate-bit arch/x86/include/asm/fpu/types.h --- a/arch/x86/include/asm/fpu/types.h~pt-xstate-bit 2015-09-16 10:48:11.570979927 -0700 +++ b/arch/x86/include/asm/fpu/types.h 2015-09-16 10:48:11.574980109 -0700 @@ -108,6 +108,7 @@ enum xfeature { XFEATURE_OPMASK, XFEATURE_ZMM_Hi256, XFEATURE_Hi16_ZMM, + XFEATURE_PT_UNIMPLEMENTED_SO_FAR, XFEATURE_MAX, }; diff -puN arch/x86/kernel/fpu/xstate.c~pt-xstate-bit arch/x86/kernel/fpu/xstate.c --- a/arch/x86/kernel/fpu/xstate.c~pt-xstate-bit 2015-09-16 10:48:11.571979973 -0700 +++ b/arch/x86/kernel/fpu/xstate.c 2015-09-16 10:48:11.575980154 -0700 @@ -469,7 +469,8 @@ static void check_xstate_against_struct( * numbers. */ if ((nr < XFEATURE_YMM) || - (nr >= XFEATURE_MAX)) { + (nr >= XFEATURE_MAX) || + (nr == XFEATURE_PT_UNIMPLEMENTED_SO_FAR)) { WARN_ONCE(1, "no structure for xstate: %d\n", nr); XSTATE_WARN_ON(1); } _