From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753283AbbIPThb (ORCPT ); Wed, 16 Sep 2015 15:37:31 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:38466 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752349AbbIPTha (ORCPT ); Wed, 16 Sep 2015 15:37:30 -0400 Date: Wed, 16 Sep 2015 20:37:20 +0100 From: Mark Brown To: Barry Song <21cnbao@gmail.com> Cc: gregkh@linuxfoundation.org, sameo@linux.intel.com, lee.jones@linaro.org, linux-kernel@vger.kernel.org, workgroup.linux@csr.com, Guo Zeng , Barry Song Message-ID: <20150916193720.GP12027@sirena.org.uk> References: <1442223610-32257-1-git-send-email-21cnbao@gmail.com> <1442223610-32257-2-git-send-email-21cnbao@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="c7qyo96SHoVh+NgR" Content-Disposition: inline In-Reply-To: <1442223610-32257-2-git-send-email-21cnbao@gmail.com> X-Cookie: You are fairminded, just and loving. User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: 94.175.94.161 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH 1/3] regmap: irq: add support for chips who have separate unmask registers X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --c7qyo96SHoVh+NgR Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Sep 14, 2015 at 09:40:08AM +0000, Barry Song wrote: > --- a/include/linux/regmap.h > +++ b/include/linux/regmap.h > @@ -800,12 +800,15 @@ struct regmap_irq { > * > * @status_base: Base status register address. > * @mask_base: Base mask register address. > + * @unmask_base: Base unmask register address. for chips who have > + * separate mask and unmask registers > * @ack_base: Base ack address. If zero then the chip is clear on read. > * Using zero value is possible with @use_ack bit. > * @wake_base: Base address for wake enables. If zero unsupported. > * @irq_reg_stride: Stride to use for chips where registers are not contiguous. > * @init_ack_masked: Ack all masked interrupts once during initalization. > * @mask_invert: Inverted mask register: cleared bits are masked out. > + * @unmask_separate: unmask is separate register from mask. We shouldn't need this - we should just be able to check if there's an unmask_base set and use that. --c7qyo96SHoVh+NgR Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJV+cTvAAoJECTWi3JdVIfQ2xgH/j5TKd+Q/x4048AbGartOWC1 K/vvBz8eD/kao78x/IocJTaXqDL0c/32RltrbbvyGKZ/wXQi8MTLpPps9VJ6OoTW 4j4DKyhY182CTfKhywLw7L+vVmF7eNHegFeCN7iWut9ipDpM9eMG4pmOjlf8sjFW jt8LNYNKOw4fR6Fv/Y45r1x4M0QtsGQa1J8s2ociw1m4ZvBc0OLFdQzsxgng/wFp JKuOtWei+aB2rWJun2S9/Yy4ehg51Un2Ob1az3FJLDuN2qk7cce9/SKjB/v2P9fF cNP1KNLyLfL5fHNHwu/UHznykgYUtmWavPNuq0vqvXKRP3LVAI8CLRA1zyYrjVg= =YfI6 -----END PGP SIGNATURE----- --c7qyo96SHoVh+NgR--