From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754669AbbIXRCD (ORCPT ); Thu, 24 Sep 2015 13:02:03 -0400 Received: from mail-bn1on0094.outbound.protection.outlook.com ([157.56.110.94]:16828 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753130AbbIXRCA (ORCPT ); Thu, 24 Sep 2015 13:02:00 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Robert.Richter@caviumnetworks.com; Date: Thu, 24 Sep 2015 19:01:38 +0200 From: Robert Richter To: Marc Zyngier , Will Deacon CC: Robert Richter , Thomas Gleixner , Jason Cooper , Tirumalesh Chalamarla , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Catalin Marinas Subject: Re: [PATCH v5 0/6] irqchip, gicv3: Updates and Cavium ThunderX errata workarounds Message-ID: <20150924170138.GI1820@rric.localdomain> References: <1442869119-1814-1-git-send-email-rric@kernel.org> <20150922175701.65ee4437@arm.com> <20150922190932.4391652a@arm.com> <20150922182726.GN7356@arm.com> <20150922204134.7491db93@arm.com> MIME-Version: 1.0 Content-Type: text/plain; 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Now with Will and Catalin on CC] > > > > > > > On Mon, 21 Sep 2015 22:58:33 +0200 > > > > Robert Richter wrote: > > > > > > > > > From: Robert Richter > > > > > > > > > > This patch series adds gicv3 updates and workarounds for HW errata in > > > > > Cavium's ThunderX GICV3. > > > > > > > > > > The patches has been rebased onto 4.3-rc1. Note that there are two > > > > > important fixes. See below for all changes. > > > > > > > > > > The first one is an unchanged resubmission of a patch from a gicv3 > > > > > series I sent a while ago. > > > > > > > > > > The next patches implement the workarounds for ThunderX's gicv3. Patch > > > > > #2 implements the cpu workaround for gicv3 on ThunderX. Patch #3 is a > > > > > prerequisit for patch #5. Patch #4 adds generic code to parse the hw > > > > > revision provided by an IIDR. This patch is used for the implementa- > > > > > tion of the actual gicv3-its workaround in #5. Patch #6 updates to the > > > > > new jump label API. > > > > > > > > > > All current review comments addressed so far with v5 > > > > > > > > Catalin, Will: assuming you don't have any objection to this series, > > > > how do you want to deal with patch 2? thanks for your review. > > What are the actual dependencies here? AFAICT, the series is addressing > > multiple errata, so would it be possible to make the arm64 bits somewhat > > independent from the gic parts? > > Patch 2 could be split into an arm64-specific part and a gic part, with > a bit of #ifdef-ery in gicv3_enable_quirks(). Patch 2 addresses a gicv3 erratum (#23154). Thus needs to be enable in host and guest, thus MIDR is used together with the arm64 errata framework. There are no other arm64 errata than this one, so it is closely related to gicv3. Or, do you mean separating arm64 code by putting the relevant parts into #ifdefs for CONFIG_ARM64? Isn't ARM_GIC_V3 only enabled for ARM64? Do you have any changes of this patch in mind? Also note that patch #6 is for #2. So if you pass the patches through different trees, put those both patches together. > > Also, I assume this is targetting 4.4? > > Up to you, really. It is not a regression, but it would still be nice > to have 4.3 working reliably on this HW. Thanks, -Robert