From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752964AbbI1VIH (ORCPT ); Mon, 28 Sep 2015 17:08:07 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:36240 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751090AbbI1VIE (ORCPT ); Mon, 28 Sep 2015 17:08:04 -0400 Date: Mon, 28 Sep 2015 14:08:01 -0700 From: Brian Norris To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Brian Norris , Daniel Vetter , Rodrigo Vivi , =?iso-8859-1?Q?St=E9phane?= Marchesin , Duncan Laurie Subject: Re: [RFC PATCH] drm/i915: PSR regressions on Broadwell Message-ID: <20150928210801.GA42029@google.com> References: <1443234373-107752-1-git-send-email-briannorris@chromium.org> <874mifm2wz.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <874mifm2wz.fsf@intel.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Sep 28, 2015 at 10:14:04AM +0300, Jani Nikula wrote: > On Sat, 26 Sep 2015, Brian Norris wrote: > > When using PSR, I see the screen freeze after only a few frames (sometimes a > > split second; sometimes it seems like practically the first frame). Bisecting > > led me to commit 3301d4092106 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT > > logic") in v4.2. This patch is the simplest fix that gets it working again for > > me, but it's probably wrong. > > > > Random thought: perhaps my panel's DPCD is programmed incorrectly? > > > > Anyway, any tips on fixing this properly? > > Here's a thought: > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index a04b4dc5ed9b..3a911d4a2308 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -274,6 +274,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) > idle_frames += 4; > } > > + idle_frames = clamp(idle_frames, 0, 15); > + > I915_WRITE(EDP_PSR_CTL(dev), val | > (IS_BROADWELL(dev) ? 0 : link_entry_time) | > max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | No dice. The VBT actually gives 0, so I just end up with the default 5 + 4 either way. > We do clamp the VBT value to range 0..15, but then go on to add to it. But this patch seems quite reasonable anyway. Acked-by: Brian Norris > Otherwise, up to Rodrigo I guess. Brian