From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
	id S1754193AbbJSPVR (ORCPT <rfc822;w@1wt.eu>);
	Mon, 19 Oct 2015 11:21:17 -0400
Received: from eu-smtp-delivery-143.mimecast.com ([146.101.78.143]:37666 "EHLO
	eu-smtp-delivery-143.mimecast.com" rhost-flags-OK-OK-OK-OK)
	by vger.kernel.org with ESMTP id S1753856AbbJSPVM convert rfc822-to-8bit
	(ORCPT <rfc822;linux-kernel@vger.kernel.org>);
	Mon, 19 Oct 2015 11:21:12 -0400
Date: Mon, 19 Oct 2015 16:21:08 +0100
From: Catalin Marinas <catalin.marinas@arm.com>
To: Ingo Molnar <mingo@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
        "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>,
        Will Deacon <will.deacon@arm.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Oleg Nesterov <oleg@redhat.com>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Andrew Morton <akpm@linux-foundation.org>
Subject: Re: Q: schedule() and implied barriers on arm64
Message-ID: <20151019152108.GC11226@e104818-lin.cambridge.arm.com>
References: <20151016151830.GZ3816@twins.programming.kicks-ass.net>
 <20151016160422.GQ3910@linux.vnet.ibm.com>
 <20151016161608.GA3816@twins.programming.kicks-ass.net>
 <CAHkRjk7z-bbTx0PyzMP0zqWxmQ4G7RrxydKQgrcigsnQEb0RBg@mail.gmail.com>
 <20151016190648.GC3816@twins.programming.kicks-ass.net>
 <20151019070604.GA17855@gmail.com>
MIME-Version: 1.0
In-Reply-To: <20151019070604.GA17855@gmail.com>
User-Agent: Mutt/1.5.23 (2014-03-12)
X-OriginalArrivalTime: 19 Oct 2015 15:21:08.0870 (UTC) FILETIME=[C7BF0A60:01D10A81]
X-MC-Unique: dFkkeqaWT1mRCGI3Y_qvvw-1
Content-Type: text/plain; charset=WINDOWS-1252
Content-Transfer-Encoding: 8BIT
Content-Disposition: inline
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, Oct 19, 2015 at 09:06:05AM +0200, Ingo Molnar wrote:
> * Peter Zijlstra <peterz@infradead.org> wrote:
> 
> > In any case, its all moot now, since Paul no longer requires schedule() to imply 
> > a full barrier.
> >
> > [...]
> 
> Nevertheless from a least-surprise POV it might be worth guaranteeing it, because 
> I bet there's tons of code that assumes that schedule() is a heavy operation and 
> it's such an easy mistake to make. Since we are so close to having that guarantee, 
> we might as well codify it?

FWIW, the arm64 __switch_to() has a heavy barrier (DSB) but the reason
for this was to cope with potentially interrupted cache or TLB
maintenance (which require a DSB on the same CPU) and thread migration
to another CPU.

-- 
Catalin