From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932247AbbJUIsa (ORCPT ); Wed, 21 Oct 2015 04:48:30 -0400 Received: from eu-smtp-delivery-143.mimecast.com ([146.101.78.143]:41216 "EHLO eu-smtp-delivery-143.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932220AbbJUIs1 convert rfc822-to-8bit (ORCPT ); Wed, 21 Oct 2015 04:48:27 -0400 Date: Wed, 21 Oct 2015 09:48:22 +0100 From: Dave Martin To: "Suzuki K. Poulose" Cc: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, Vladimir.Murzin@arm.com, steve.capper@linaro.org, ryan.arnold@linaro.org, ard.biesheuvel@linaro.org, aph@redhat.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, edward.nevill@linaro.org, james.morse@arm.com, andre.przywara@arm.com, marc.zyngier@arm.com, christoffer.dall@linaro.org Subject: Re: [PATCHv4 08/24] arm64: Keep track of CPU feature registers Message-ID: <20151021084821.GE4801@e103592.cambridge.arm.com> References: <1445261101-22344-1-git-send-email-suzuki.poulose@arm.com> <1445261101-22344-9-git-send-email-suzuki.poulose@arm.com> MIME-Version: 1.0 In-Reply-To: <1445261101-22344-9-git-send-email-suzuki.poulose@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 21 Oct 2015 08:48:22.0830 (UTC) FILETIME=[3E1E34E0:01D10BDD] X-MC-Unique: gn2IQVAKQOq75Y41VkAq_g-1 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: 8BIT Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 19, 2015 at 02:24:45PM +0100, Suzuki K. Poulose wrote: > This patch adds an infrastructure to keep track of the CPU feature > registers on the system. For each register, the infrastructure keeps > track of the system wide safe value of the feature bits. Also, tracks > the which fields of a register should be matched strictly across all > the CPUs on the system for the SANITY check infrastructure. [...] > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index 85507fe..af0c187 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -35,6 +35,37 @@ > > #include > > +/* CPU feature register tracking */ > +enum ftr_type { > + FTR_EXACT, /* Use a predefined safe value */ > + FTR_LOWER_SAFE, /* Smaller value is safe */ > + FTR_HIGHER_SAFE,/* Bigger value is safe */ > +}; > + > +#define FTR_STRICT true /* SANITY check strict matching required */ > +#define FTR_NONSTRICT false /* SANITY check ignored */ > + > +struct arm64_ftr_bits { > + bool strict; /* CPU Sanity check: strict matching required ? */ > + enum ftr_type type; > + u8 shift; > + u8 width; > + s64 safe_val; /* safe value for discrete features */ > +}; > + > +/* > + * @arm64_ftr_reg - Feature register > + * @strict_mask Bits which should match across all CPUs for sanity. nit: ^ whitespace, no need to fix unless respinning the series > + * @sys_val Safe value across the CPUs (system view) > + */ > +struct arm64_ftr_reg { [...] Cheers ---Dave