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Date: Fri, 30 Oct 2015 17:32:40 +0000
From: Mark Rutland <mark.rutland@arm.com>
To: Brijesh Singh <brijeshkumar.singh@amd.com>
Cc: devicetree@vger.kernel.org, arnd@arndb.de, pawel.moll@arm.com,
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Subject: Re: [PATCH v4] EDAC: Add ARM64 EDAC
Message-ID: <20151030173240.GJ31073@leverpostej>
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> > > * Interaction with firmware
> > > - When/do we handle interrupts?
> > 
> > We can a properties in dt bindings:
> > 
> > 1) "num-interrupts = 1" - number of interrupt count. One interrupts per cluster
> >     e.g if you have 4 cluster then num-interrupts=4.
> > 2) interrupts = <0, 92, 0> <0, 94, 0> <0, 96, 0> <0, 98, 0>  // interrupt mapping
> > 
> > If num-interrupts = 0, then firmware handles interrupts. Optionally we can use HEST FIRMWARE-FIRST
> > bit, if bit is set then firmware is handling the interrupt otherwise use DT information.
> 
> You won't have the HEST and DT information at the same time, given that
> at runtime the kernel uses one of ACPI or DT.

>>From a quick look at the HEST definition, I don't doesn't seem like it's
possible to describe this feature -- there's no error source descriptor
for it and the generic hardware error source is not applicable.

So I'm worried that it may not be possible to use this feature with
ACPI.

Thanks,
Mark.