From: Peter Zijlstra <peterz@infradead.org>
To: gratian.crisan@ni.com
Cc: Thomas Gleixner <tglx@linutronix.de>,
linux-kernel@vger.kernel.org, Ingo Molnar <mingo@redhat.com>,
"H . Peter Anvin" <hpa@zytor.com>,
x86@kernel.org, Borislav Petkov <bp@alien8.de>,
Josh Cartwright <joshc@ni.com>,
gratian@gmail.com
Subject: Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error
Date: Mon, 9 Nov 2015 23:02:32 +0100 [thread overview]
Message-ID: <20151109220232.GO17308@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1447099142-10220-1-git-send-email-gratian.crisan@ni.com>
On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.crisan@ni.com wrote:
> The Intel Xeon E5 processor family suffers from errata[1] BT81:
> +#ifdef CONFIG_X86_TSC
> + /*
> + * Xeon E5 BT81 errata: TSC is not affected by warm reset.
> + * The TSC registers for CPUs other than CPU0 are not cleared by a warm
> + * reset resulting in a constant offset error.
> + */
> + if ((c->x86 == 6) && (c->x86_model == 0x3f))
> + set_cpu_bug(c, X86_BUG_TSC_OFFSET);
> +#endif
That's hardly a family, that's just one, Haswell server.
next prev parent reply other threads:[~2015-11-09 22:02 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-09 19:59 gratian.crisan
2015-11-09 22:02 ` Peter Zijlstra [this message]
[not found] ` <CAKA=qzarnUUmZb7DQE+u0Dei3F+FQNoL2bak_-dV9D9+3L=itQ@mail.gmail.com>
2015-11-10 18:27 ` Josh Hunt
2015-11-10 19:47 ` Gratian Crisan
2015-11-10 20:41 ` Josh Hunt
2015-11-11 15:41 ` Gratian Crisan
2015-11-13 20:43 ` Peter Zijlstra
2015-11-17 16:38 ` Gratian Crisan
2015-11-19 19:04 ` Gratian Crisan
2015-11-13 21:13 ` Dave Hansen
2015-11-17 16:49 ` Gratian Crisan
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