From: "Lothar Waßmann" <LW@KARO-electronics.de>
To: Duan Andy <fugang.duan@freescale.com>
Cc: Andrew Lunn <andrew@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Fabio Estevam <Fabio.Estevam@freescale.com>,
Kevin Hao <haokexin@gmail.com>,
Lucas Stach <l.stach@pengutronix.de>,
Philippe Reynes <tremyfr@gmail.com>,
Russell King <rmk+kernel@arm.linux.org.uk>,
Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
Stefan Agner <stefan@agner.ch>
Subject: Re: [PATCH] net: fec: fix enet_out clock handling
Date: Mon, 30 Nov 2015 07:56:17 +0100 [thread overview]
Message-ID: <20151130075617.0f880cd1@ipc1.ka-ro> (raw)
In-Reply-To: <BN3PR0301MB1219C4D8E1B09F1AE27E18FAF5020@BN3PR0301MB1219.namprd03.prod.outlook.com>
Hi,
> From: Lothar Waßmann <LW@KARO-electronics.de> Sent: Friday, November 27, 2015 9:39 PM
> > To: Andrew Lunn; David S. Miller; Estevam Fabio-R49496; Kevin Hao; Lothar
> > Waßmann; Lucas Stach; Duan Fugang-B38611; Philippe Reynes; Russell King;
> > Uwe Kleine-König; linux-kernel@vger.kernel.org; netdev@vger.kernel.org;
> > Stefan Agner
> > Subject: [PATCH] net: fec: fix enet_out clock handling
> >
> > When ENET_OUT is being used as reference clock for an external PHY, the
> > clock must not be disabled while the PHY is active. Otherwise the PHY may
> > lose its internal state and require a reset to become functional again.
> >
> > A symptom for this bug is a network interface that constantly toggles
> > between UP and DOWN state:
> > fec 800f0000.ethernet eth0: Link is Up - 100Mbps/Full - flow control
> > rx/tx fec 800f0000.ethernet eth0: Link is Down fec 800f0000.ethernet eth0:
> > Link is Up - 100Mbps/Full - flow control rx/tx fec 800f0000.ethernet eth0:
> > Link is Down [...]
> >
> > Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
> > ---
> > drivers/net/ethernet/freescale/fec_main.c | 34 +++++++++++++------------
> > ------
> > 1 file changed, 14 insertions(+), 20 deletions(-)
> >
>
> When MAC is not ready with clocks disabled, it is not necessary to supply clock for PHY. In fact, PHY also is not ready, why does it need clock ?
> For your problem, you must add PHY reset in your dts file to resolve your problem.
>
The phy-reset-gpio property is set in the DTB. But fec_reset_phy()
which asserts the RESET is only called from within the probe() function.
It should probably be called from fec_restart() instead?
Lothar Waßmann
next prev parent reply other threads:[~2015-11-30 6:57 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-27 13:39 Lothar Waßmann
2015-11-27 15:16 ` Michael Heimpold
2015-11-28 13:13 ` Duan Andy
2015-11-28 16:43 ` Andrew Lunn
2015-11-30 1:46 ` Duan Andy
2015-11-30 1:58 ` Andrew Lunn
2015-11-30 6:56 ` Lothar Waßmann [this message]
2015-11-30 7:31 ` Duan Andy
2015-11-30 2:07 ` Andrew Lunn
2015-11-30 5:37 ` Lothar Waßmann
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