From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753160AbcAIEle (ORCPT ); Fri, 8 Jan 2016 23:41:34 -0500 Received: from mail-oi0-f53.google.com ([209.85.218.53]:34387 "EHLO mail-oi0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751284AbcAIElc (ORCPT ); Fri, 8 Jan 2016 23:41:32 -0500 Date: Fri, 8 Jan 2016 22:41:30 -0600 From: Andy Gross To: Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH] arm64: dts: Add L2 cache node to msm8916 Message-ID: <20160109044130.GA20052@hector.attlocal.net> References: <1452297429-6382-1-git-send-email-sboyd@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452297429-6382-1-git-send-email-sboyd@codeaurora.org> User-Agent: Mutt/1.5.23.1 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 08, 2016 at 03:57:09PM -0800, Stephen Boyd wrote: > The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the > dtsi file so that the cache hierarchy can be probed. > > Cc: > Signed-off-by: Stephen Boyd > --- Reviewed-by: Andy Gross