From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753556AbcALUag (ORCPT ); Tue, 12 Jan 2016 15:30:36 -0500 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:50175 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753510AbcALUae (ORCPT ); Tue, 12 Jan 2016 15:30:34 -0500 Date: Tue, 12 Jan 2016 21:30:02 +0100 From: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= To: Lothar =?iso-8859-1?Q?Wa=DFmann?= Cc: Russell King - ARM Linux , Mark Rutland , Andrew Lunn , Stefan Agner , Greg Ungerer , Nimrod Andy , Jeff Kirsher , Sascha Hauer , devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , Richard Cochran , Rob Herring , linux-arm-kernel@lists.infradead.org, Fabio Estevam , Kevin Hao , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Sascha Hauer , Kumar Gala , Lucas Stach , Shawn Guo , "David S. Miller" , Philippe Reynes Subject: Re: [PATCHv2 0/2] net: fec: Reset ethernet PHY whenever the enet_out clock is being enabled Message-ID: <20160112203002.GZ24441@pengutronix.de> References: <1452611876-451-1-git-send-email-LW@KARO-electronics.de> <20160112152405.GZ19062@n2100.arm.linux.org.uk> <20160112170444.11c412c5@ipc1.ka-ro> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20160112170444.11c412c5@ipc1.ka-ro> User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, On Tue, Jan 12, 2016 at 05:04:44PM +0100, Lothar Waßmann wrote: > > On Tue, Jan 12, 2016 at 04:17:54PM +0100, Lothar Waßmann wrote: > > > This patchset fixes a regression introduced by > > > commit e8fcfcd5684a ("net: fec: optimize the clock management to save power") > > > for ethernet PHYs that are using ENET_OUT as reference clock (on i.MX6 or i.MX28) > > > > > > Changes vs. v1: > > > - fixed reference to the commit that introduced the regression. > > > - dropped patch to use gpiod framework. This should be added later, > > > after the affected DTBs have been updated to specify the correct > > > gpio_flags. > > > > > > Patch overview: > > > 1. cleanup patch to remove redundant NULL checks > > > 2. call fec_reset_phy() after the ENET_OUT clock has been enabled > > > > I definitely want to test these on my SolidRun boards before these get > > merged: the AR8035 on there is configured via pin-straps, and then > > further tweaked with PHY quirks. Resetting with the iMX6 in the > > wrong state may result in the AR8035 being reconfigured (even jumping > > to a different MDIO address) and certainly would need the PHY quirks > > re-running. > > > As far as I can tell, all SolidRun boards do not specify the enet_out > clock in the dtb, so the PHY reset behaviour should be unaffected by > this patch on those boards, since the additional fec_reset_phy() call is > framed by: > if (fep->clk_enet_out) { > ... > } > > But verifying this explicitly is of course a good idea. If the SolidRun boards don't do this, this doesn't mean it's safe in general. The problem is real, isn't it? Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ |