From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752756AbcAMPwY (ORCPT ); Wed, 13 Jan 2016 10:52:24 -0500 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:52150 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751076AbcAMPwV (ORCPT ); Wed, 13 Jan 2016 10:52:21 -0500 Date: Wed, 13 Jan 2016 15:51:54 +0000 From: Mark Brown To: Laxman Dewangan Cc: Krzysztof Kozlowski , robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linus.walleij@linaro.org, gnurou@gmail.com, lee.jones@linaro.org, a.zummo@towertech.it, alexandre.belloni@free-electrons.com, lgirdwood@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, rtc-linux@googlegroups.com, swarren@nvidia.com, treding@nvidia.com, Mallikarjun Kasoju Message-ID: <20160113155154.GN6588@sirena.org.uk> References: <5695A854.60108@samsung.com> <5696378B.6070704@nvidia.com> <20160113115736.GJ6588@sirena.org.uk> <56963D8D.9060908@nvidia.com> <20160113123133.GK6588@sirena.org.uk> <5696451F.3000707@nvidia.com> <20160113130909.GL6588@sirena.org.uk> <56964CEF.3030900@nvidia.com> <20160113142023.GM6588@sirena.org.uk> <56966242.4080601@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="wCvMePosDEf3szVw" Content-Disposition: inline In-Reply-To: <56966242.4080601@nvidia.com> X-Cookie: APL hackers do it in the quad. User-Agent: Mutt/1.5.24 (2015-08-30) X-SA-Exim-Connect-IP: 2a01:348:6:8808:fab::3 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH V2 6/6] regulator: max77620: add regulator driver for max77620/max20024 X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --wCvMePosDEf3szVw Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Jan 13, 2016 at 08:12:10PM +0530, Laxman Dewangan wrote: > On Wednesday 13 January 2016 07:50 PM, Mark Brown wrote: > >On Wed, Jan 13, 2016 at 06:41:11PM +0530, Laxman Dewangan wrote: > >>On Wednesday 13 January 2016 06:39 PM, Mark Brown wrote: > >>>What is "it" and why can't we check what the current configuration is > >>>while setting FPS to NONE? > >>I will have platform specific data in callback of enable/disable only. > >>Which call back do I need to set this? enable/disable or post register? > >I'm sorry but I can't parse what you're saying here. > Here, before machine constraint applies, I need to configure FPS on desired > source. I'm a bit confused here - I had thought you needed things the other way around? Can you describe in concrete terms what you want to configure? > >>>>I need to set the FPS src properly for each rails before callback happen > >>>>from regulator init so that enable/disable/is_enable can handle it properly. > >>>Why not just reorder the callback so it happens before the constraints > >>>are applied? > >>which callback I need to reorder for getting the context for configruation? > >The existing call to parse the DT. > Are we allow to do i2c transfer in the existing callback for parsing the DT? Yes, of course. --wCvMePosDEf3szVw Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJWlnKZAAoJECTWi3JdVIfQuTAH/2xoPMUPjm/TIKnibYdD8Pas DVtt7ufLP8+4/52m2te6EEtgHl1lFsqoTtvNyUMORjeY9Uv5aWXubNXFy2Je1vnr xplbYaIWV6tVzuFsfQABE000P3HEarIxWvvZImRQ187g0VDjDmsLbI7XrzIDJofd EdBeuCecL12RH1tOeQBUtagsZaWvMd1UWspmVUjmLp8MlrLVndHz6ZmkEIk17xdl 6SIya8u8IFyB3+URQ9aRwiSH5CE0Rsm7kRT/PThbXWwfnnMSCUZimi7/6mHqvrFO OZS70XvOR+1n/ekkdPrd6YSWSsYenlfGy5H42muCLmw1VEbXdEK/uBHhoyG6D4k= =rJk0 -----END PGP SIGNATURE----- --wCvMePosDEf3szVw--