From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752977AbcAUUFh (ORCPT ); Thu, 21 Jan 2016 15:05:37 -0500 Received: from shards.monkeyblade.net ([149.20.54.216]:48277 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751258AbcAUUFd (ORCPT ); Thu, 21 Jan 2016 15:05:33 -0500 Date: Thu, 21 Jan 2016 12:05:32 -0800 (PST) Message-Id: <20160121.120532.2109574129268460718.davem@davemloft.net> To: jszhang@marvell.com Cc: thomas.petazzoni@free-electrons.com, mw@semihalf.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, sebastian.hesselbarth@gmail.com, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 0/4] net: mvneta: support more than one clk From: David Miller In-Reply-To: <1453289245-2061-1-git-send-email-jszhang@marvell.com> References: <1453289245-2061-1-git-send-email-jszhang@marvell.com> X-Mailer: Mew version 6.7 on Emacs 24.5 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.5.12 (shards.monkeyblade.net [149.20.54.216]); Thu, 21 Jan 2016 12:05:33 -0800 (PST) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jisheng Zhang Date: Wed, 20 Jan 2016 19:27:21 +0800 > Some platforms may provide more than one clk for the mvneta IP, for > example Marvell BG4CT provides "core" clk for the mac core, and "axi" > clk for the AXI bus logic. > > This series tries to addess the "more than one clk" issue. Note: to > support BG4CT, we have lots of refactor work to do, eg. BG4CT doesn't > have mbus concept etc. > > Since v2: > - Name the optional clock as "bus", which is a bit more flexible. > > Since v1: > - Add Thomas Acks to patch1 and patch2. > - make sure the headers are really sorted (some headers are still > unsorted in v1). > - disable axi clk before disabling core clk, Thank Thomas. > - update dt binding as Thomas suggested. Series applied, thanks.