From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967422AbcA1LP0 (ORCPT ); Thu, 28 Jan 2016 06:15:26 -0500 Received: from foss.arm.com ([217.140.101.70]:59430 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967219AbcA1LPV (ORCPT ); Thu, 28 Jan 2016 06:15:21 -0500 Date: Thu, 28 Jan 2016 11:14:53 +0000 From: Mark Rutland To: Suravee Suthikulpanit , will.deacon@arm.com, robin.murphy@arm.com Cc: robh+dt@kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, arm@kernel.org, brijeshkumar.singh@amd.com, thomas.lendacky@amd.com, leo.duran@amd.com Subject: Re: [PATCH 11/13] dtb: amd: Add PCIe SMMU device tree node Message-ID: <20160128111453.GG17123@leverpostej> References: <1453929121-12171-1-git-send-email-Suravee.Suthikulpanit@amd.com> <1453929121-12171-12-git-send-email-Suravee.Suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1453929121-12171-12-git-send-email-Suravee.Suthikulpanit@amd.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jan 27, 2016 at 03:11:59PM -0600, Suravee Suthikulpanit wrote: > From: Suravee Suthikulpanit > > Add PCIe SMMU device tree node for AMD Seattle SOC. > > Signed-off-by: Suravee Suthikulpanit > --- > arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi > index a7fc059..bfccfea 100644 > --- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi > +++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi > @@ -210,6 +210,7 @@ > device_type = "pci"; > bus-range = <0 0x7f>; > msi-parent = <&v2m0>; > + #stream-id-cells = <16>; > reg = <0 0xf0000000 0 0x10000000>; > > interrupt-map-mask = <0xf800 0x0 0x0 0x7>; > @@ -230,6 +231,28 @@ > <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>; > }; > > + pcie0_smmu: smmu@e0a00000 { > + compatible = "arm,mmu-401"; > + reg = <0 0xe0a00000 0 0x10000>; > + #global-interrupts = <1>; > + interrupts = /* Uses combined intr for both > + * global and context > + */ > + <0 333 4>, > + <0 333 4>; > + /* Note: > + * SID[2:0] = PCIe function number > + * SID[7:3] = PCIe device number > + * SID[14:8] = PCIe bus number > + */ > + mmu-masters = <&pcie0 > + /* 1:00:[0,3] */ 256 257 258 259 > + /* 2:00:[0,3] */ 512 513 514 515 > + /* 3:00:[0,3] */ 768 769 770 771 > + /* 4:00:[0,3] */ 1024 1025 1026 1027 > + >; > + }; This doesn't look right to me. I didn't think that RID->SID mapping was actually defined by any binding, so (how) are these numbers used? I'm uncomfortable with this, given we should be moving towards the generic IOMMU binding (and then we'd use the iommu-map binding [1] for this). Will, Robin, thoughts? Mark. [1] https://lkml.org/lkml/2015/7/23/561