From: Daniel Vetter <daniel@ffwll.ch>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Lyude <cpaul@redhat.com>, Rob Clark <rclark@redhat.com>,
David Airlie <airlied@linux.ie>,
Benjamin Tissoires <btissoir@redhat.com>,
intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
Daniel Vetter <daniel.vetter@intel.com>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/skl: Fix typo in DPLL_CFGCR1 definition
Date: Tue, 9 Feb 2016 10:47:32 +0100 [thread overview]
Message-ID: <20160209094732.GJ11240@phenom.ffwll.local> (raw)
In-Reply-To: <20160204161128.GO23290@intel.com>
On Thu, Feb 04, 2016 at 06:11:28PM +0200, Ville Syrjälä wrote:
> On Thu, Feb 04, 2016 at 10:43:21AM -0500, Lyude wrote:
> > We accidentally point both cfgcr registers for the second shared DPLL to
> > the same location in i915_reg.h. This results in a lot of hw pipe state
> > mismatches whenever we try to do a modeset that requires allocating the
> > DPLL to a CRTC:
> >
> > [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr1 (expected 0x80000168, found 0x000004a5)
> > [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 108000, found 49500)
> > [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 108000, found 49500)
> >
> > This usually ends up causing blank monitors, since the DPLL never can
> > get set to the right clock.
> >
> > Fixes: f0f59a00a1 ("drm/i915: Type safe register read/write")
>
> Actually
> Fixes: 086f8e84a085 ("drm/i915: Prefix raw register defines with underscore")
>
> That's the second regression from the type safety stuff :( I guess we
> still don't have enough testing coverage since this has gone undetected
> for so long.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
>
> > Signed-off-by: Lyude <cpaul@redhat.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 007ae83..b9a564b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7514,7 +7514,7 @@ enum skl_disp_power_wells {
> > #define DPLL_CFGCR2_PDIV_7 (4<<2)
> > #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
> >
> > -#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR2)
> > +#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> > #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
> >
> > /* BXT display engine PLL */
> > --
> > 2.5.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
prev parent reply other threads:[~2016-02-09 9:47 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-04 15:43 Lyude
2016-02-04 16:11 ` [Intel-gfx] " Ville Syrjälä
2016-02-09 9:47 ` Daniel Vetter [this message]
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