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Date: Tue, 16 Feb 2016 23:22:19 +0900
From: Namhyung Kim <namhyung@kernel.org>
To: Jiri Olsa <jolsa@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>, Jiri Olsa <jolsa@kernel.org>,
        lkml <linux-kernel@vger.kernel.org>, David Ahern <dsahern@gmail.com>,
        Ingo Molnar <mingo@kernel.org>,
        Peter Zijlstra <a.p.zijlstra@chello.nl>
Subject: Re: [PATCHv2 5/5] perf tools: Add perf data cache feature
Message-ID: <20160216142219.GA6286@danjae.kornet>
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Hi Jiri,

On Tue, Feb 16, 2016 at 01:11:30PM +0100, Jiri Olsa wrote:
> On Sun, Feb 14, 2016 at 05:03:46PM +0100, Jiri Olsa wrote:
> > Storing CPU cache details under perf data. It's stored
> > as new HEADER_CACHE feature and it's displayed under
> > header info with -I option:
> > 
> >   $ perf report --header-only -I
> >   ...
> >   # cache info:
> >   #  L1 Data 32K [0-1]
> >   #  L1 Instruction 32K [0-1]
> >   #  L1 Data 32K [2-3]
> >   #  L1 Instruction 32K [2-3]
> >   #  L2 Unified 256K [0-1]
> >   #  L2 Unified 256K [2-3]
> >   #  L3 Unified 4096K [0-3]
> >   ...
> > 
> 
> changing the output based on Ingo's comment
> v2 attached, the rest of the patchset stays
> 
> my perf/cache branch is updated
> 
> thanks,
> jirka
> 
> 
> ---
> Storing CPU cache details under perf data. It's stored
> as new HEADER_CACHE feature and it's displayed under
> header info with -I option:
> 
>   $ perf report --header-only -I
>   ...
>   # CPU cache info:
>   #  L1 Data                 32K [0-1]
>   #  L1 Instruction          32K [0-1]
>   #  L1 Data                 32K [2-3]
>   #  L1 Instruction          32K [2-3]
>   #  L2 Unified             256K [0-1]
>   #  L2 Unified             256K [2-3]
>   #  L3 Unified            4096K [0-3]
>   ...
> 
> All distinct caches are stored/displayed.
> 
> Link: http://lkml.kernel.org/n/tip-byxl1gwto8z9d5hyozprtaty@git.kernel.org
> Signed-off-by: Jiri Olsa <jolsa@kernel.org>
> ---

[SNIP]
> +static int build_caches(struct cache_level caches[], u32 size, u32 *cntp)
> +{
> +	u32 i, cnt = 0;
> +	long ncpus;
> +	u32 nr, cpu;
> +	u16 level;
> +
> +	ncpus = sysconf(_SC_NPROCESSORS_CONF);
> +	if (ncpus < 0)
> +		return -1;
> +
> +	nr = (u32)(ncpus & UINT_MAX);
> +
> +	for (cpu = 0; cpu < nr; cpu++) {
> +		for (level = 0; level < 10; level++) {
> +			struct cache_level c;
> +			int err;
> +
> +			err = cache_level__read(&c, cpu, level);
> +			if (err < 0)
> +				return err;
> +
> +			if (err == 1)
> +				break;
> +
> +			for (i = 0; i < cnt; i++) {
> +				if (cache_level__cmp(&c, &caches[i]))
> +					break;
> +			}
> +
> +			if (i == cnt)
> +				caches[cnt++] = c;

			else
				cache_level__free(&c);
???

Thanks,
Namhyung


> +
> +			if (WARN_ONCE(cnt == size, "way too many cpu caches.."))
> +				goto out;
> +		}
> +	}
> + out:
> +	*cntp = cnt;
> +	return 0;
> +}